TMS320UC5405 datasheet(23/77 Pages) TI

23 / 77 page

Functional Overview

October 2002 − Revised October 2004

SPRS199B

3.2

On-Chip Peripherals

The UC5405 device supports the following on-chip peripherals:

•

Software-programmable wait-state generator with programmable bank-switching wait states

•

An enhanced 8-bit host-port interface (HPI8)

•

Two multichannel buffered serial ports (McBSPs)

•

Two hardware timers

•

A clock generator with a phase-locked loop (PLL)

•

A direct memory access (DMA) controller

3.2.1 Software-Programmable Wait-State Generator

The software wait-state generator of the UC5405 can extend external bus cycles by up to 14 machine cycles.

Devices that require more than 14 wait states can be interfaced using the hardware READY line. When all

external accesses are configured for zero wait states, the internal clocks to the wait-state generator are

automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the

UC5405.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs

of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to

5 separate address ranges. This allows a different number of wait states for each of the five address ranges.

Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)

defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is

initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown

in Figure 3−5 and described in Table 3−2.

XPA

I/O

DATA

R/W-0

R/W-111

DATA

PROGRAM

R/W-111

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3−5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

TMS320UC5405 Datasheet(PDF) 23 Page - Texas Instruments