TMS320UC5405 datasheet(71/77 Pages) TI

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Electrical Specifications

October 2002 − Revised October 2004

SPRS199B

Table 6−30. HPI8 Mode Switching Characteristics

PARAMETER

MIN

MAX

UNIT

ten(DSL-HD)

Enable time, HD driven from DS low

Case 1a: Memory accesses when

DMAC is active in 16-bit mode and

tw(DSH) < 18H†

18H + 21 − tw(DSH)

Case 1b: Memory accesses when

DMAC is active in 16-bit mode and

tw(DSH) ≥ 18H†

td(DSL-HDV1)

Delay time, DS low to HDx valid for

first byte of an HPI read

Case 1c: Memory access when

DMAC is active in 32-bit mode and

tw(DSH) < 26H†

26H + 21 − tw(DSH)

td(DSL-HDV1)

Delay time, DS low to HDx valid for

first byte of an HPI read

Case 1d: Memory access when

DMAC is active in 32-bit mode and

tw(DSH) ≥ 26H†

Case 2a: Memory accesses when

DMAC is inactive and tw(DSH) < 10H†

10H + 21 − tw(DSH)

Case 2b: Memory accesses when

DMAC is inactive and tw(DSH) ≥ 10H†

Case 3: Register accesses

td(DSL-HDV2)

Delay time, DS low to HDx valid for second byte of an HPI read

th(DSH-HDV)R

Hold time, HDx valid after DS high, for a HPI read

tv(HYH-HDV)

Valid time, HDx valid after HRDY high

td(DSH-HYL)

Delay time, DS high to HRDY low (see Note 1)

Case 1a: Memory accesses when

DMAC is active in 16-bit mode†

18H + 21

td(DSH-HYH)

Delay time, DS high to HRDY high

Case 1b: Memory accesses when

DMAC is active in 32-bit mode†

26H + 21

td(DSH-HYH)

Delay time, DS high to HRDY high

Case 2: Memory accesses when

DMAC is inactive†

10H + 21

Case 3: Write accesses to HPIC

6H + 21

td(HCS-HRDY)

Delay time, HCS low/high to HRDY low/high

td(COH-HYH)

Delay time, CLKOUT high to HRDY high

td(COH-HTX)

Delay time, CLKOUT high to HINT change

td(COH-GPIO)

Delay time, CLKOUT high to HDx output change. HDx is configured as a

general-purpose output.

NOTES:

1. The HRDY output is always high when the HCS input is high, regardless of DS timings.

2. This timing applies to the first byte of an access, when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes

to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.

† DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are

affected by DMAC activity.

TMS320UC5405 Datasheet(PDF) 71 Page - Texas Instruments

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