TMS320UC5405 datasheet(22/77 Pages) TI

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Functional Overview

October 2002 − Revised October 2004

SPRS199B

TMS320UC5405

SRAM

D15 − D0

A5 − A0

PS or DS

D0 − D9

D15 − D0

A5 − A0

A6 − A15

Q0 − Q9

Figure 3−3. TMS320UC5405 External Memory Paging Scheme

3.1.5 Relocatable Interrupt Vector Table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch

instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate

interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.

However, these vectors can be remapped to the beginning of any 128-word page in program space after

device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see

Figure 3−4) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or

trap vector is mapped to the new 128-word page.

NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

IPTR

R/W

IPTR

MP/MC

OVLY

AVIS

DROM

CLKOFF

SMUL

SST

R/W

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3−4. Processor Mode Status (PMST) Register

TMS320UC5405 Datasheet(PDF) 22 Page - Texas Instruments