TMS320UC5405 datasheet(27/77 Pages) TI

27 / 77 page

Functional Overview

October 2002 − Revised October 2004

SPRS199B

The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers

are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with

the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an

HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC

3.2.2.2

Multichannel Buffered Serial Ports

The UC5405 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that

allow direct interface to other C54x/LC54x DSPs, codecs, and other devices in a system. The McBSPs are

based on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP

provides:

•

Full-duplex communication

•

Double-buffered data registers, which allow a continuous data stream

•

Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

•

Direct interface to:

−

T1/E1 framers

−

MVIP switching compatible and ST-BUS compliant devices

−

IOM-2 compliant devices

−

Serial peripheral interface devices

•

Multichannel transmit and receive of up to 128 channels

•

A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

•µ-law and A-law companding

•

Programmable polarity for both frame synchronization and data clocks

•

Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external

interface of each McBSP consists of the following pins:

•

BCLKX

Transmit reference clock

•

BDX

Transmit data

•

BFSX

Transmit frame synchronization

•

BCLKR

Receive reference clock

•

BDR

Receive data

•

BFSR

Receive frame synchronization

The six pins listed are functionally equivalent to the previous serial port interface pins in the TMS320C5000



platform of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX

and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit

structure allows DXR to be loaded with the next word to be sent while the transmission of the current word

is in progress.

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,

respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received

on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register

(RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until

the DRR is available. This structure allows storage of the two previous words while the reception of the current

word is in progress.

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP

interrupts, event signals, and status flags. The DMA is capable of handling data movement between the

McBSPs and memory with no intervention from the CPU.

TMS320C5000 is a trademark of Texas Instruments.

TMS320UC5405 Datasheet(PDF) 27 Page - Texas Instruments

TMS320UC5405 Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL