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TMS320UC5405 Datasheet(PDF) 63 Page - Texas Instruments |
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TMS320UC5405 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 77 page ![]() Electrical Specifications 63 October 2002 − Revised October 2004 SPRS199B Table 6−18. McBSP Transmit and Receive Switching Characteristics† PARAMETER MIN MAX UNIT tc(BCKRX) Cycle time, BCLKR/X BCLKR/X int 4H ns tw(BCKRXH) Pulse duration, BCLKR/X high BCLKR/X int D − 3‡ D + 2‡ ns tw(BCKRXL) Pulse duration, BCLKR/X low BCLKR/X int C − 3‡ C + 2‡ ns td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR int −3 6 ns td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR ext 7 13 ns td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX int 0 6 ns td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX ext 5 19 ns tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data BCLKX int 1 6 ns tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit of transfer BCLKX ext 7 13 ns td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid DXENA = 0§ BCLKX int 0¶ 6 ns td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid DXENA = 0§ BCLKX ext 5 19 ns td(BFXH-BDXV) Delay time, BFSX high to BDX valid BFSX int 1¶ 2 ns td(BFXH-BDXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode BFSX ext 7 18 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ T = BCLKRX period = (1 + CLKGDV) * 2H C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320UC5405. ¶ Minimum delay times also represent minimum output hold times. |
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