RT3050 datasheet(34/235 Pages) ETC1

34 / 235 page

RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-34-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

Note: Ther e is no special H/W function related to the

setting of this bit. That means the firmware could use it for

other purposes (as a general purpose bootstrapping).

INIC_8MB_SDRAM

0: SDRAM configuration is 2MB for iNIC

1: SDRAM configuration is 8MB for iNIC

Note : There is no special H/W function related to the

setting of this bit. That means the firmware could use it for

other purposes (as a general purpose bootstrapping).

Bootstrap

27:26

Reserved

2’b0

25:24

GE0_MODE

Gigabit Port Mode

2’b00 : RGMII Mode (10/100/1000M bps)

2’b01 : MII Mode (10/100 Mbps)

2’b10 : Reversed MII Mode (10/100 Mbps)

2’b11 : Reserved

2’b00

Reserved

1’b0

BOOT_ADDR

0 : CPU boots at address 0x1FC00000

1 : CPU boots at address 0x1F000000

1’b0

RO-

BYPASS_PLL

0: Not bypass PLL

1: Bypass PLL

Bootstrap

BIG_ENDIAN

0: Little endian

1: Big endian

Bootstrap

Reserved

1’b0

CPU_CLK_SEL

0: 320Mhz

1: 384 Mhz

Note : System clock is 1/3 of the CPU CLK

Bootstrap

17:16

BOOT_FRO M

2’b00 : boot from external 16-bit flash (default)

2’b01 : boot from external 8-bit flash

2’b10 : boot from external NAND flash

2’b11 : boot from internal ROM

Bootstrap

15:8

R/W

TEST_CODE[7:0]

Probe signals selection

Default value is from bootstrap and can by modify by

software

Bootstrap

7:4

Reserved

7’b0

3:2

SRAM_CS_MODE

2’b00: Normal SRAM chip select output (active low)

2’b01: Watch dog reset output (active low for 3 system

clocks)

2’b10: BT coexistence signal “WLAN_ACT” output

2’b11: Reserved.

Note : These two bits are write only. The read value is

always 2’b00.

2’b00

Reserved

1’b0

SDRAM_CLK_DRV

1’b0 : 8mA SDRAM_CLK driving

1’b1 : 12mA SDRAM_CLK driving

Note : This bit is write only. The read value is always 1’b0.

1’b0

Reserved register (offset: 0x14)

Bits

Type

Name

Description

Initial value

31:0

Reserved

32’b0

TESTSTAT: Firmware Test Status Register (offset: 0x18)

Bits

Type

Name

Description

Initial value

31:0

R/W

TSETSTAT[31:0]

Firmware Test Status

Note: This register is reset only by power on reset.

32’b0

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