RT3050 datasheet(68/235 Pages) ETC1

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RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-68-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

3.11 SPI Controller

3.11.1 Features



Supports SPI master operations



Programmable clock polarity



Programmable interface clock rate



Programmable bit ordering



Firmware-controlled SPI enable



Programmable payload (address + data) length

3.11.2 Block Diagram

Fig. 3-11-1 SPI controller Block Diagram

3.11.3 Register Description (base: 0x1000.0B00)

SPISTAT: SPI Interface Status (offset: 0x00)

Bits

Type

Name

Description

Initial value

31:2

Reserved

30’b0

BUSY

SPI transfer in progress

0: The SPI interface is inactive.

1: An SPI transfer is in progress.

Note: This bit must be ‘0’ before initiating a transfer. Any

attempt to start a data transfer will be ignored if this bit is a ‘1’.

1’b0

SPICFG: SPI Interface Configuration (offset: 0x10)

Bits

Type

Name

Description

Initial value

31:9

Reserved

23’b0

R/W

MSBFIRST

Bit transfer order

0: LSB bits of data sent/received first.

1: MSB bits of data sent/received first.

Note: This bit applies to both the command and data.

1’b1

Reserved

1’b0

R/W

SPICLKPOL

SPI clock default state

0: The default state of the SPICLK is logic ‘0’.

1: The default state of the SPICLK is logic ‘1’.

Note: This bit is ignored if the SPI interface block is a slave

(SPISLAVE bit is set).

1’b0

R/W

RXCKEDGE

SPI clock default state

0: Data is captured on the rising edge of the SPICLK signal.

1: Data is captured on the falling edge of the SPICLK signal.

1’b0

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