RT3050 datasheet(64/235 Pages) ETC1

64 / 235 page

RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-64-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

3.10 I2C Controller

3.10.1 Features



Two I2C Host Controllers



Programmable I2C bus clock rate



Supports the Synchronous Inter Integrated Circuits (I2C) serial protocol



Bi-directional data transfer



Programmable address width up to 8 bits



Sequential byte read or write capability



Device address and data address can be transmitted for device, page and address selection



Supports Standard mode and Fast mode

3.10.2 Block Diagram

Fig. 3-10-1 I2C controller Block Diagram

3.10.3 Register Description (base: 0x1000.0900)

CONFIG: I2C Configuration Register (offset: 0x00)

Bits

Type

Name

Description

Initial value

31:8

Reserved

24’b0

7:5

R/W

ADDRLEN [2 :0]

Address Length

The value written to this register plus one will indicate the

number of address bits to be transferred from the I2C ADDR

etc.)

3’b0

4:2

R/W

DEVADLEN [2:0]

Device Address Length

The value written to this register plus one indicates the

number of device address bits to be transferred from the

DEVADDR r egister. This field should be programmed to ‘6’ for

compliance with I2C bus protocol.

3’b0

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