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RT3050 Datasheet(PDF) 77 Page - List of Unclassifed Manufacturers |
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RT3050 Datasheet(HTML) 77 Page - List of Unclassifed Manufacturers |
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77 / 235 page  RT3050/52 Datasheet Preliminary Revision August 14, 2008 DSR3050/52_V.2.0_081408 -77- Form No.：QS-073-F02 Rev.：1 Kept by： DCC Ret. T ime： 5 Years PCM_CFG: PCM_CFG Register (offset: 0x04) Bits Type Name Description Initial value 31 RW EXT_CLK_EN PCM_CLK is generated by ex ternal source. 1: PCM_CLK is provided by external 0: PCM_CLK is generated by internal clock divider 0 30 RW CLKOUT_EN Enable the PCM_CLK_O UT 1: PCM_CLK_OUT should be free run 0: PCM_CLK_OUT should be pull -low forever. (NOTE: Nor mally, the register should be asserted to ‘1’. And it should be asserted after divider cfg & divider clock enable) 0 29:28 - - Reserved 27 RW EXT_FSYNC FSYNC is provided by external. 1: FSYNC is provided by external 0: FSYNC is generated by internal circuit. 0 26 RW LONG_FSYNC FSYNC mode: 1: long FSYNC 0: short FSYNC 0 25 RW FSYNC_POL Polarity of FSYNC 1: FSYNC is high active 0: FSYNC is low active 1 24 RW DRX_TRI Tristate the DRX as fall edge as LSB bit. 1: Tristate the DRX 0: non- Tristate the DRX 1 23:3 - - Reserved 0 2:0 RW SLOT_MODE How many slot each PCM frame 0: 4 slots, PCM clock out/in should be 256KHz. 1: 8 slots, PCM clock out/in should be 512KHz. 2:16 slots, PCM clock out/in should be 1.024MHz. 3:32 slots, PCM clock out/in should be 2.048MHz. 4:64 slots, PCM clock out/in should be 4.096MHz. 5:128 slots, PCM clock out/in should be 8.192MHz. other: r eserved. Note: When using the external cl ock, the frequency clock should be equal to PCM_clock out. Otherwise, the PCM_CLKin should be 8.192 MHz. 0 INT_STATUS: INT_STATUS Register (offset: 0x08) Bits Type Name Description Initial value 31:16 RO - Reserved 0 15 RW CH1T_DMA_ FAULT Found any fault of the CH1-TX’s DMA signals. (Write ‘1’ to clear) 0 14 RW CH1T_O VRUN The FIFO of CH1-TX overrun(Write ‘1’ to clear) 13 RW CH1T_UNRUN The FIFO of CH1-TX underrun(Write ‘1’ to clear) 0 12 RW CH1T_THRES The FIFO of CH1-TX lower than the defined thr eshol d. (Write ‘1’ to clear) 0 11 RW CH1R_DMA_ FAULT Found any fault of the CH1-RX’s DMA signals. (Write ‘1’ to clear) 0 10 RW CH1R_OVRUN The FIFO of CH1-RX overrun(Write ‘1’ to clear) 9 RW CH1R_UNRUN The FIFO of CH1-RX underrun(Write ‘1’ to clear) 0 8 RW CH1R_THRES The FIFO of CH1-RX lower than the defined threshold. (Write ‘1’ to clear) 0 7 RW CH0T_DMA_ FAULT Found any fault of the CH0-TX’s DMA signals. (Write ‘1’ to clear) 0 6 RW CH0T_O VRUN The FIFO of CH0-TX overrun(Write ‘1’ to clear) |
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