RT3050 datasheet(84/235 Pages) ETC1

84 / 235 page

RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-84-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

R/W

TWR

Write Recovery time number of system clock cycles – 1.

1’b1

27:24

R/W

TMRD

LOAD MODE to any other command delay number of system clock

cycles – 1.

4’b0001

23:20

R/W

TRFC

AUTO REFRESH period number of system clock cycles – 1.

4’b1001

19:18

Reserved

2’b00

17:16

R/W

TCAS

READ command to data valid delay (CAS latency) in number of

system clock cycles – 1.

2’b10

15:12

R/W

TRAS

ACTIVE to PRECHARGE command delay in number of system clock

cycles – 1.

4’b0101

11:10

Reserved

2’b00

9:8

R/W

TRCD

ACTIVE to READ or WRITE delay in number of system clock cycles –

2’b10

7:4

R/W

TRC

ACTIVE to ACTIVE command period in number of system clock

cycles -1

4’b1000

3:2

Reserved

2’b00

1:0

R/W

TRP

PRECHARGE command period in number of system clock cycles –1. 2’b10

SDRAM_CFG1: SDRAM Configuration 1 (offset: 0x04)

Bits

Type

Name

Description

Initial value

R/W

SDRAM_INIT_S

TART

Write 1 to perform SDRAM initialization sequence.

Can not set it to zero after initialization.

1’b0

SDRAM_INIT_

DONE

0: SDRAM has not been initialized

1: SDRMA has been initialized

1’b0

R/W

RBC_MAPPING

1 : {ROW ADDR, BANK ADDR, COL ADDR}

address mapping scheme

0 : {BANK ADDR, ROW ADDR, COL ADDR}

address mapping scheme

1’b0

29:25

Reserved

5’b0

R/W

SDRAM_WIDT

Number of SDRAM data bus bits :

0 : 16 bits

1 : 32 bits (default)

1’b1

23:22

Reserved

2’b0

21:20

R/W

NUMCOLS

Number of Column address bits :

0 : 8 Column address bits

1 : 9 Column address bits (default)

2 : 10 Column address bits

3: 11 Column address bits

2’b01

19:18

Reserved

2’b00

17:16

R/W

NUMROWS

Number of Row address bits :

0 : 11 Row address bits

1 : 12 Row address bits (default)

2 : 13 Row address bits

3: 14 Row address bits (not allocable if boot from NAND flash is

enabled)

2’b10

15:0

R/W

TREFR

AUTO REFRESH period in number of SDRAM clock cycles – 1.

16’h0600

*PS: SDRAM Self Refresh Mode and Power Down will be supported later.

FLASH_CFG0 : Flash Bank 0 Configuration (offset: 0x08)

Bits

Type

Name

Description

Initial value

31:28

Reserved

4’b0

27:26

FLASH_WIDTH

Number of Flash Chip Select0 data bus bits :

0 : 8 bits

1 : 16 bits (default)

2 : reserved

2’b01

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