RT3050 datasheet(38/235 Pages) ETC1

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RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-38-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

3.5 Timer

3.5.1

Features



Independent clock pre-scale for each timer



Independent interrupts for each timer



Two General-purpose timers



Periodic mode



Free-running mode



Time-out mode



Second timer may be used as watchdog timer



Watchdog timer resets system on time-out

3.5.2

Block Diagram

Fig. 3-5-1 Timer Block Diagram

3.5.3

TMRSTAT: Timer Status Register (offset: 0x00)

Bits

Type

Name

Description

Initial value

31:6

Reserved

26’b0

TMR1RST

Timer 1 Reset

Writing a ‘1’ to this bit will reset the Timer 1 to 0xFFFF if in

free-running mode, or the value specified in the TMR1 LOAD

Writing a ‘0’ to this bit has no effect. Reading this bit will

return a ‘0’.

1’b0

TMR0RST

Timer 0 Reset

Writing a ‘1’ to this bit will reset Timer 0 to 0xFFFF if in

free-running mode, or the value specified in the

1’b0

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