RT3050 datasheet(49/235 Pages) ETC1

49 / 235 page

RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-49-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

R/W

FORCEPAR

Force Parity Bit

0: Normal functionality.

1: If even parity is selected, the (transmitted and checked)

parity is forced to '0'; if odd parity is selected, the (transmitted

and checked) parity if forced to '1'.

1’b0

R/W

EPS

Even Parity Select

0: Odd parity selected (checksum, including parity is '1').

1: Even parity selected (checksum, including parity is '0').

Note: This bit is ignored if the PEN bit is '0'.

1’b0

R/W

PEN

Parity Enable

0: Parity is not transmitted or checked.

1: Parity is generated (transmit), and checked (receive).

1’b0

R/W

STB

Stop Bit Select

0: 1 stop bit is transmitted and received.

1: 1.5 stop bits are transmitted and received if WLS is '0'; 2 stop

bits are transmitted and received if WLS is '1', '2', or '3'.

1’b0

1:0:

R/W

WLS[1:0]

Word Length Select

0: Each character is 5 bits in length

1: Each character is 6 bits in length

2: Each character is 7 bits in length

3: Each character is 8 bits in length

2’b0

MCR: Modem Control Register (offset: 0x18)

Bits

Type

Name

Description

Initial value

31:5

Reserved

24’b0

R/W

LOOP

Loop-back Mode Enable

0: Normal Operation.

1: The UART is put into loop-back mode, used for self-test: The

TXD pin is driven high; the TXD signal connections are made

internally

Signal

Wrapped back through…

TXD

RXD

DTRN

DSRN

RTSN

CTSN

OUT1N

RIN

OUT2N

DCDN

1’b0

R/W

OUT2

Out2 Value

0: OUT2 N pin is driven to a high level.

1: OUT2 N pin is driven to a low level.

Note: This bit is only functional in loop-back mode.

R/W

OUT1

Out1 Value

0: OUT1 N pin is driven to a high level.

1: OUT1 N pin is driven to a low level.

Note: This bit is only functional in loop-back mode.

R/W

RTS

Out1 Value

0: RTSN pin is driven to a high level.

1: RTSN pin is driven to a low level.

1’b0

R/W

DTR

Reserved

0: DTRN pin is driven to a high level.

1: DTRN pin is driven to a low level.

1’b0

LSR: Line Status Register (offset: 0x1C)

Bits

Type

Name

Description

Initial value

31:8

Reserved

24’b0

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