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RT3050 Datasheet(PDF) 71 Page - List of Unclassifed Manufacturers

Part # RT3050
Description  Dual Band Concurrent Router
PDF  235 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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RT3050 Datasheet(HTML) 71 Page - List of Unclassifed Manufacturers

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RT3050/52
Datasheet
Preliminary
Revision August 14, 2008
DSR3050/52_V.2.0_081408
-71-
Form No.：QS-073-F02
Rev.：1
Kept by： DCC
Ret. T ime： 5 Years
3.12 Generic DMA Controller
3.12.1 Features
Support 8 DMA channels
Support 8 DMA r equests
Programmable hardware channel priority
Programmable DMA Burst Size (1,2,4,8,16 burst transfer)
Support 32 bit wide transaction
Big-endian and Little-endian support
Support memory to memory, memory to peripheral, peripheral to memory, peripheral to
peripheral transfers.
Interrupts for each channel. They also can be masked, independently.
Each channel transaction can be masked temporarily by the software, and rel eased by the
hardware automatically.
3.12.2 Block Diagram
DMA Engine
Rbus
Master
Rbus
Master
Arbiter
Pbus
Slave
Ch0
Ch7
Mux
Interrupt
Controller
Rbus Interface
(Master)
Pbus Interface
(Slave)
Rbus Interface
(Master)
DMA
Interface
Interrupt
Interface
Fig. 3-12-1 Generic DMA controller Block Diagram
3.12.3 Register Description (base: 0x10000700)
GDMASAn: GDMA Channel n Source Address (offset: 0x00, 0x10, 0x20, 0x3 0, 0x40, 0x50, 0x60, 0x70 ) (n:0~7)
Bits
Type
Name
Description
Initial value
31:0
R/W
CHANNEL
SOURCE
ADDRESS
Channel Source Address:
This register contains the source address information
32’b0
GDMADAn: GDMA Channel n Destination Address (offset: 0x04, 0x 14, 0x24, 0x34, 0x44, 0x54, 0x64, 0x74 ) (n:0~7)
Bits
Type Name
Description
Initial value
31:0
R/W
CHANNEL
DESTINATION
ADDRESS
Channel Destination Address:
This register contains the destination address information
32’b0



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