M263 datasheet(267/398 Pages) NUVOTON

267 / 398 page

M261/M262/M263

Mar 25, 2020

Page 267 of 398

Rev 1.02

Cortex

® -M23 processor features:



Arm

® v8-M Baseline architecture.



Arm

® v8-M Baseline Thumb® -2 instruction set that combines high code density with 32-bit

performance.



Support for single-cycle I/O access.



Power control optimization of system components.



Integrated sleep modes for low power consumption.



Optimized code fetching for reduced Flash and ROM power consumption.



A 32-bit Single cycle Hardware multiplier.



A 32-bit Hardware divider.



Deterministic, high-performance interrupt handling for time-critical applications.



Deterministic instruction cycle timing.



Support for system level debug authentication.



Support for Arm

® Debug Interface Architecture ADIv5.1 Serial Wire Debug (SWD).



ETM for instruction trace.



Separated privileged and unprivileged modes.



Protected Memory System Architecture (PMSAv8) Memory Protection Units (MPU).



SysTick timer.



A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor with

up to 240 interrupts.

M263 Datasheet(PDF) 267 Page - Nuvoton Technology Corporation

M263 Datasheet(HTML) 267 Page - Nuvoton Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL