M263 datasheet(268/398 Pages) NUVOTON

268 / 398 page

M261/M262/M263

Mar 25, 2020

Page 268 of 398

Rev 1.02

6.2

System Manager

6.2.1

Overview

System management includes the following sections:



System Reset



System Power Distribution



SRAM Memory Orginization



System Timer (SysTick)



Nested Vectored Interrupt Controller (NVIC)



System Control register

6.2.2

Reset

The system reset can be issued by one of the events listed below. These reset event flags can be

read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from

peripheral signals. Software reset can trigger reset through setting control registers.



Hardware Reset Sources

–

Power-on Reset (POR)

–

Low level on the nRESET pin

–

Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)

–

Low Voltage Reset (LVR)

–

Brown-out Detector Reset (BOD Reset)

–

CPU Lockup Reset



Software Reset Sources

–

CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])

–

System Reset to reboot but keeping the booting setting from APROM or LDROM by

writing 1 to SYSRESETREQ (AIRCR[2])

–

CPU Reset for Cortex

® -M23 core only by writing 1 to CPURST (SYS_IPRST0[1])

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