NTP53X2 datasheet(3/133 Pages) NXP

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NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

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Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

3 / 133

2 Features and benefits

• Reading distance with long-range reader > 60 cm (> 25 inches)

• Zero-power readout of an I2C sensor

• Adjustable security levels up to mutual AES authentication (NTP5332 only)

• Flexible split between three open and/or protected memory areas

• Ensured authenticity of product through value chain

• Interoperable data exchange according to NFC Forum standards

• Energy-efficient design with reduced bill of material

• Interoperable and high performance NFC interface

– ISO/IEC 15693 and NFC Forum Type 5 Tag compliant

– 64-bit Unique IDentifier

• Reliable and robust memory

– 2048 bytes (16384 bits) user EEPROM on top of configuration memory

– 256 bytes (2048 bits) SRAM for frequently changing data and pass-through mode

– 40 years data retention

– Write endurance of 1 000 000 cycles

• Configurable contact interface

– I2C slave standard (100 kHz) and fast (400 kHz) mode

– NTP5332 offers a Transparent I2C master channel (for example, read sensors

without an MCU)

– One configurable event detection pin

– Two GPIOs as multiplexed I2C lines

– Two Pulse Width Modulation (PWM) channels as multiplexed GPIOs and/or ED pin

– 1.62 V to 5.5 V supply voltage

• Scalable security for access and data protection

– Disable NFC interface temporarily

– Disable I2C interface temporarily

– NFC PRIVACY mode

– Read-only protection as defined in NFC Forum Type 5 Tag Specification

– Full, read-only, or no memory access based on 32-bit password from both interfaces

– Optional 64-bit password protection from NFC perspective

– 128-bit AES authentication as defined in ISO/IEC 15693 for NTP5332

– ECC-based reprogrammable originality signature

• Multiple fast data transfer mode

– Pass-through mode with 256 byte SRAM buffer

– Standardized data transfer mode (PHDC, TNEP)

• Low-power budget application support

– Energy harvesting with configurable output voltage up to 30 mW

– Low-power standby current typically <6 µA

– Hard power down current typically <0.25 µA

• Very robust architecture

– -40 °C to 105 °C for EEPROM read, SRAM and register access

– -40 °C to 85 °C for EEPROM write access

• Extensive product support package

– Feature specific application notes

– Development board including software and source code

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