NTP53X2 datasheet(12/133 Pages) NXP

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NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

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Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

12 / 133

8 Functional description

8.1 Memory Organization

8.1.1 General

The entire memory is divided into three different parts:

• User memory

– This part of the memory is intended to be used to store user data. It is organized in

blocks of 4 bytes each (see Section 8.1.2).

– According to NFC Forum Type 5 Tag Specification, EEPROM block 0 contains the

Capability Container directly followed by the NDEF Message TLV. If NTAG 5 link is

used in a proprietary way, any user data may be stored in the user memory. Direct

read/write access with the standard READ BLOCK and WRITE BLOCK commands

(see Section 8.2.3.5) to this part of the memory is possible depending on the related

security and write protection conditions.

– 16-bit counter

The last block of the EEPROM memory from NFC perspective contains the 16-bit

counter and the counter protection flag (see Section 8.1.2.1). This counter is not

accessible from I2C perspective.

• Configuration area

– Within this part of the memory all configuration options are stored (see Section 8.1.3).

This memory area can only be accessed with the READ CONFIG (see

Section 8.2.3.2.1) or WRITE CONFIG (see Section 8.2.3.2.2) commands from NFC

perspective. From I2C perspective, normal READ and WRITE commands are used.

– The configuration area contains required security-related information, such as access

keys with related privileges, headers, customer ID (CID), originality signature and

many more which will be loaded at power-on reset.

– Access to configuration blocks may be blocked at all or password protected with

related configuration bits.

– All session registers are accessible in the configuration area as long as not locked

by LOCK_SESSION_REG. These configuration items can be changed on the fly and

have immediate effect, but get lost after power-on reset.

• SRAM

– SRAM is accessible when NTAG 5 link is VCC supplied and SRAM_ENABLE is set to

1b.

– Volatile SRAM can be used for fast and frequent data transfer (see Section 8.1.5).

With WRITE SRAM (see Section 8.2.3.6.2) and READ SRAM (see Section 8.2.3.6.1),

the content is written or read.

– When the SRAM gets mapped to user memory (the start address is always block 0

from both interfaces), then standard READ BLOCK and WRITE BLOCK commands

can be used. This mechanism is used, e.g., for PHDC or dynamic pairing.

– From I2C perspective, SRAM is always located from address 2000h to 203Fh.

WARNING: The content of bytes and bits defined as RFU SHALL NOT be changed.

8.1.2 User memory

According to NFC Forum Type 5 Tag Specification, the user accessible EEPROM

memory is divided into blocks. A block is the smallest access unit. For NTAG 5 link,

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