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NTP53X2 Datasheet(PDF) 30 Page - NXP Semiconductors

Part # NTP53X2
Description  NTAG 5 link - NFC Forum-compliant I2C bridge
PDF  133 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

NTP53X2 Datasheet(HTML) 30 Page - NXP Semiconductors

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NXP Semiconductors
NTP53x2
NTAG 5 link - NFC Forum-compliant I2C bridge
NTP53x2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.3 — 3 July 2020
COMPANY PUBLIC
544533
30 / 133
Table 33. I2C Memory organization example
Block
Byte 0
Byte 1
Byte 2
Byte 3
Description
0000h
0001h
0002h
...
...
...
...
...
004Eh
004Fh
AREA_0-L
0050h
0051h
:
:
:
:
:
01FEh
AREA_0-H
01FFh
RFU
Note: Counter
page from NFC
perspective
If the protection pointer address is set to block 0, then the entire user memory is defined
as AREA_0-H.
The protection pointer address and protection pointer configuration can be only changed
under following conditions:
• I2C Key Header Configuration status is "Not Active"
• I2C Key Header Configuration status is "Active and read/write after authentication" with
read and write privilege key I2C authentication has been executed before successfully.
The protection pointer address and protection pointer configuration cannot be changed
when I2C configuration status is "Active and Locked". This status is irreversible.
Configuration area and SRAM access can be protected by I2C authentication when
related bits in SRAM_CONF_PROT are set to 1b.
The default value of I2C_PPC is 00h. Which means full access to AREA_0-L and
AREA_0-H.
Table 34. I2C Protection Pointer Configuration (I2C_PPC)
Bit
Name
Value Description
7
RFU
0b
6
RFU
0b
0b
AREA_0-H is not write protected
5
WRITE_AREA_H
1b
AREA_0-H is write protected
0b
AREA_0-H is not read protected
4
REA_AREA_H
1b
AREA_0-H is read protected
3
RFU
0b
2
RFU
0b
0b
AREA_0-L is not write protected
1
WRITE_AREA_L
1b
AREA_0-L is write protected



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