NTP53X2 datasheet(100/133 Pages) NXP

100 / 133 page

NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

100 / 133

NTAG 5 link supports the I2C protocol defined in UM10204. Any device that sends data

onto the bus is defined as a transmitter, and any device that reads the data from the bus

is defined as a receiver. The device that controls the data transfer is known as the "bus

master", and the other as the "slave" device. A data transfer can only be initiated by the

bus master, which will also provide the serial clock for synchronization.

8.3.1.1.1 Start condition

Start is identified by a falling edge of Serial Data (SDA), while Serial Clock (SCL) is

stable in the high state. A Start condition must precede any data transfer command.

NTAG 5 link continuously monitors SDA (except during a Write cycle) and SCL for a Start

condition, and will not respond unless one is given.

8.3.1.1.2 Stop condition

Stop is identified by a rising edge of SDA while SCL is stable and driven high. A Stop

condition terminates communication between NTAG 5 link and the bus master. A Stop

condition at the end of a Write command triggers the internal write cycle.

8.3.1.1.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,

whether it is the bus master or slave device, releases Serial Data (SDA) after sending 8

bits of data. During the ninth clock pulse period, the receiver pulls Serial Data (SDA) low

to acknowledge the receipt of the 9th data bits.

8.3.1.1.4 Data input

During data input, the IC samples SDA on the rising edge of SCL. For correct device

operation, SDA must be stable during the rising edge of SCL, and the SDA signal must

change only when SCL is driven low.

8.3.1.1.5 Addressing

To start communication between a bus master and NTAG 5 link, the bus master must

initiate a Start condition. Following this initiation, the bus master sends the device

address. The IC address from I2C consists of a 7-bit device identifier (see Table 229 for

default value).

As long as I2C address is 7 bit long, the 8th bit (least significant bit) is used as the Read/

Write bit (R/W). This bit is set to 1b for Read and 0b for Write operations.

If a match occurs on the device address, the IC gives an acknowledgment on SDA during

the 9th bit time. If the IC does not match the device select code, it deselects itself from

the bus and clears the register I2C_IF_LOCKED (see Table 88).

Table 229. Default NTAG 5 I2C address from I2C

Device address

Value

1 [1]

0 [1]

1 [1]

0 [1]

1 [1]

0 [1]

[1]

Initial values - can be changed.

The I2C address of NTAG 5 link (Configuration Byte) can be modified by the NFC and I2C

interface.

NTP53X2 Datasheet(PDF) 100 Page - NXP Semiconductors

NTP53X2 Datasheet(HTML) 100 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL