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NTP53X2 Datasheet(PDF) 49 Page - NXP Semiconductors |
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NTP53X2 Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 133 page  NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 49 / 133 Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 Remark A4h 10A4h PWM0_ON_OFF_REG PWM1 Configuration (see Section 8.1.4.5) A5h 10A5h PWM1_ON_OFF_REG PWM1 Configuration (see Section 8.1.4.5) A6h 10A6h WDT_CONFIG_REG RFU Watch Dog Timer Configuration (see Section 8.1.4.6) A7h 10A7h EH_CONFIG_REG RFU Energy Harvesting Configuration (see Section 8.1.4.7) A8h 10A8h ED_CONFIG_REG RFU Event detection functionality (see Section 8.1.4.8) A9h 10A9h I2C_SLAVE_CONFIG_REG RFU I2C Slave Configuration (see Section 8.1.4.9) AAh 10AAh RESET_ GEN_REG RFU Reset Register (see Section 8.1.4.10) ABh 10ABh ED_INTR_ CLEAR_REG RFU Clear Event Detection (see Section 8.1.4.11) ACh 10ACh I2C_M_S_ ADD_REG I2C_M_LEN_REG RFU RFU I2C Master Configuration (see Section 8.1.4.12) ADh 10ADh I2C_M_ STATUS_REG RFU I2C Master Configuration (see Section 8.1.4.12) AEh 10AEh RFU AFh 10AFh RFU 8.1.4.1 Status register Different status of NTAG 5 link can be known by reading status register. The status register can be read by READ_CONFG. Some of the registers may be cleared. Setting status bits to 1b is not possible at all. Table 86. Status Register Location Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 A0h 10A0h STATUS0_REG STATUS1_REG RFU |
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