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TMS320F28075PZP Datasheet(PDF) 88 Page - Texas Instruments |
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TMS320F28075PZP Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 192 page  7.10.1.2.3 ADCEXTSOC Timing Requirements MIN(1) MAX UNIT tw(INT) Pulse duration, INT input low/high Synchronous 2tc(SYSCLK) cycles With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles (1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1. 7.10.1.2.4 ADC Input Model Note ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA. 7.10.1.2.4.1 Single-Ended Input Model Parameters DESCRIPTION VALUE Cp Parasitic input capacitance See Table 7-8 Ron Sampling switch resistance 600 Ω Ch Sampling capacitor 16.5 pF Rs Nominal source impedance 50 Ω ADC Ron Switch VREFLO Ch Cp ADCINx AC Rs Figure 7-31. Single-Ended Input Model TMS320F28076, TMS320F28075 SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021 www.ti.com 88 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28076 TMS320F28075 |
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