LT3477 datasheet(9/26 Pages) AD

9 / 26 page

LT3950

Rev. 0

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PIN FUNCTIONS

32mV of hysteresis when returning over 1.25V, switching

stops and the part shuts down. Drive this pin high with

a logic level greater than 1.4V or low with a logic level

below 1V for simple ON/OFF functionality, or tie it through

a resistive voltage divider to VIN for a precise input under-

voltage shutdown threshold.

VIN: Input Supply Pin. Must be locally bypassed.

PWMTG: High Side Gate Driver for External Series PMOS

Switch. This pin is used to disconnect the load for PWM

dimming as well as fault events. PWMTG drives the PMOS

gate between VISP and VISP – 7.5V (typ.) to cut off the

flow of residual charge from the output capacitor when

the load should be disconnected, as well as to prevent the

long transient that would result from needing to recharge

the output capacitor at the end of a long PWM off period.

Leave open if unused. The voltage at PWMTG is limited

to 7.5V (typ.) below the voltage at ISP to protect the gate

of the PMOS switch.

SW: Switch Pin. See PCB recommendations in the

Applications section for details on reducing EMI.

GND (Exposed Pad): This is the ground connection. Must

be soldered to PCB ground for the device to work.

LT3477 Datasheet(PDF) 9 Page - Analog Devices