LT3477 datasheet(21/26 Pages) AD

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LT3950

Rev. 0

For more information www.analog.com

TYPICAL APPLICATIONS

100k

LT3950

INTVCC

3950 TA02

1µF

2.2µF

20k

FAULT

PWMTG

PWM

CTRL

INTVCC

SYNC/SPRD

ISP

ISN

2.2µF

LED ARRAY

2MHz

45.3k

4.7k

VIN

EN/UVLO

GND

10µH

500m

1µF

220pF

INTVCC

500mA

VIN

3V TO

48V

L1: WURTH 74437324100

D1: DIODES INC. DFLS260Q

M1: VISHAY SI7309

5W Buck-Boost Mode LED Driver with Spread Spectrum Frequency Modulation

Efficiency and Power Loss

ILED = 0.5A

ILED = 0.25A

ILED = 0.5A

ILED = 0.25A

VIN (V)

16 20 24 28 32 36 40 44 48

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

3950 TA02b

connect to the external PMOS switch, if used. Note, how-

ever, that the gate of the external PMOS should be con-

nected by a narrow trace. Except for the external PMOS

gate, avoid vias where possible in the power path. If vias

are truly unavoidable, use many (more than 10) in parallel.

Despite the techniques used in the design of LT3950 to

mitigate electromagnetic interference (EMI), proper PCB

layout is critical for suppressing radiated and conducted

noise. Minimizing the area of the SW node will decrease

the amount of capacitance that the switch sees, and thus

reduce the current spike seen during switching events.

Failing to minimize the area of the so-called hot loop will

dramatically degrade EMI performance. Keep the output

capacitor and catch diode as close as possible to the SW

pin of the IC to minimize the hot loop. For more informa-

tion about hot loops see Analog Devices Application Notes

AN136 and AN139.

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