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LT3950

Rev. 0

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The EN/UVLO threshold has a hysteretic window to pre-

vent oscillating between the ON and OFF states. When

the EN/UVLO pin falls below its falling threshold (1.25V

typ.), switching stops, soft-start is reset, and if an exter-

nal PMOS is used according to instructions in the PWM

Dimming section, the load is disconnected from the out-

put capacitor.

Low Voltage (SEPIC) Startup

Certain power stage topologies, such as the SEPIC, may

require the part to start up in the condition where ISP and

ISN are both near (or at) 0V. This condition is handled dif-

ferently than steady-state operation. Below around 2.5V at

ISN, the part does not use the programmed offset defined

by the CTRL pin, but instead uses a constant offset of

around 85mV (typ.) across ISP and ISN. This ensures

that the part starts in a reasonable amount of time. When

ISN < 2.5V (typ), LED Open and LED Short faults are

disabled. The ability of the error amplifier to tolerate an

input common mode voltage of 0V should not lead the

user to consider low-side sensing. Not only is the LED

current sense amplifier most accurate above 4V on ISN,

but also recall that ISP provides the positive rail for the

driver of the external disconnect PMOS. Therefore the use

of low side sensing of LED current is not recommended.

Full-scale threshold accuracy is derated when VISN < 4V.

Planning for Thermal Shutdown

The LT3950 will automatically shut down when the inter-

nal temperature is above 170°C. This shutdown is guar-

anteed to always be outside of the operating region of the

device. The effects of thermal shutdown are similar to that

of certain load faults: switching stops, soft-start is reset,

and if an external PMOS is used according to instructions

in the PWM Dimming section, the load is disconnected

from the output capacitor.

The exposed pad of LT3950 is ground, and must be sol-

dered to a good, large ground plane with many vias to aid

in thermal management. A simple electrical connection

is not sufficient for high-power operation, good thermal

conductivity is critical.

PCB Layout Guidelines and Information

Printed Circuit Board (PCB) layout profoundly affects per-

formance of all power applications. Proper electrical and

thermal connection between the IC and outside world will

make or break any system. Do not neglect the thoughtful

and detailed layout of any application PCB.

The exposed ground pad on the bottom of the package

is the only path to ground for the IC, and it will not work

correctly unless the exposed pad has a good, high-quality

solder connection to a ground plane. The ground con-

nection for analog functions such as RT, the compensa-

tion network, and any voltage dividers for PWM or CTRL

should be Kelvin connected to the exposed pad. A sepa-

rate power ground should exist for the input and output

capacitors and LED load. If possible, the INTVCC bypass

capacitor should have its own ground.

Proper power and ground planes provide both electrical

and thermal connections between the IC and the outside

world. It is imperative that at least one ground plane be

present in any application of LT3950. Ground planes

should not be interrupted by other traces, and should be

continuous, very wide sheets of copper. If components

connect to the ground plane by way of vias, use filled vias

if possible. Connect the exposed pad of the IC to such a

ground plane. Use as many vias as will fit in the exposed

pad area to make the connection. Use filled vias if pos-

sible. Do not copy any particular layout for the exposed

pad connection, but instead use as many vias as will fit

given the capabilities of the PCB manufacturer.

In addition to soldering down the exposed pad, it is critical

to provide a good, robust layout for the rest of the power

path. Use wide traces for VIN and to connect to the load.

Keep the sense resistor very close to the IC, and ensure

that the ISP and ISN traces run as close to one another

as possible. It is strongly recommended to not allow ISP

and ISN to take different paths to the sense resistor, but

instead to keep them beside one another as much as pos-

sible. Minimize the total area of any SW node traces; keep

the output capacitor and external catch diode as close as

possible to the IC to help this. Finally, use wide traces to

APPLICATIONS INFORMATION

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