AT90PWM2 datasheet(142/365 Pages) ATMEL

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142

AT90PWM2/3

4317A-3–AVR–02/05

Fifty Percent Waveform

Configuration

When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to con-

figure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it

duplicates the OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRn-

RAH/L registers. So it is not necessary to program OCRnSAH/L and OCRnRAH/L

registers.

Update of Values

To avoid unasynchronous and incoherent values in a cycle, if an update of one of sev-

eral values is necessary, all values are updated at the same time at the end of the cycle

by the PSC. The new set of values is calculated by sofware and the update is initiated

by software.

Figure 65. Update at the end of complete PSC cycle.

The software can stop the cycle before the end to update the values and restart a new

PSC cycle.

Value Update Synchronization

New timing values can be written during the PSC cycle. Thanks to LOCK and

AUTOLOCK configuration bits, the new whole set of values can be taken into account

after the end of the PSC cycle.

When AUTOLOCK configuration bit is set, the update of the PSC internal registers will

be done at the end of the PSC cycle if the Output Compare Register RB has been the

last written.

When LOCK configuration bit is set, there is no update. The update of the PSC internal

registers will be done at the end of the PSC cycle if the LOCK bit is released to zero.

When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.

See “PSC 0 Configuration Register – PCNF0” on page 171

Software

PSC

Regulation Loop

Calculation

Writting in

PSC Registers

Cycle

With Set i

Cycle

With Set i

Cycle

With Set i

Cycle

With Set i

Cycle

With Set j

End of Cycle

Request for

an Update

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