AT90PWM2 datasheet(205/365 Pages) ATMEL

205 / 365 page

205

AT90PWM2/3

4317B–AVR–02/05

The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition.

A Data OverRun occurs when the receive buffer is full (two characters), it is a new char-

acter waiting in the Receive Shift Register, and a new start bit is detected. If the DOR

flag is set there was one or more serial frame lost between the frame last read from

UDR, and the next frame read from UDR. For compatibility with future devices, always

write this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame

received was successfully moved from the Shift Register to the receive buffer.

The following example (See Figure 102.) represents a Data OverRun condition. As the

receive buffer is full with CH1 and CH2, CH3 is lost. When a Data OverRun condition is

detected, the OverRun error is memorized. When the two characters CH1 and CH2 are

read from the receive buffer, the DOR bit is set (and not before) and RxC remains set to

warn the application about the overrun error.

Figure 102. Data OverRun example

The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Par-

ity Error when received. If Parity Check is not enabled the UPE bit will always be read

zero. For compatibility with future devices, always set this bit to zero when writing to

UCSRA. For more details see “Parity Bit Calculation” on page 197 and “Parity Checker”

on page 205.

Parity Checker

The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type

of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When

enabled, the Parity Checker calculates the parity of the data bits in incoming frames and

compares the result with the parity bit from the serial frame. The result of the check is

stored in the receive buffer together with the received data and stop bits. The Parity

Error (UPE) flag can then be read by software to check if the frame had a Parity Error.

The UPE bit is set if the next character that can be read from the receive buffer had a

Parity Error when received and the Parity Checking was enabled at that point (UPM1 =

1). This bit is valid until the receive buffer (UDR) is read.

CH1

CH2

CH3

RxD

RxC

DOR

Software Access

to Receive buffer

RxC=1

UDR=CH1

DOR=0

RxC=1

UDR=CH2

DOR=0

RxC=1

UDR=XX

DOR=1

AT90PWM2 Datasheet(PDF) 205 Page - ATMEL Corporation

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