AT90PWM2 datasheet(206/365 Pages) ATMEL

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206

AT90PWM2/3

4317B–AVR–02/05

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from

ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero)

the Receiver will no longer override the normal function of the RxD port pin. The

Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in

the buffer will be lost

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer

will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed

during normal operation, due to for instance an error condition, read the UDR I/O loca-

tion until the RXC flag is cleared.

The following code example shows how to flush the receive buffer.

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

Asynchronous Data

Reception

The USART includes a clock recovery and a data recovery unit for handling asynchro-

nous data reception. The clock recovery logic is used for synchronizing the internally

generated baud rate clock to the incoming asynchronous serial frames at the RxD pin.

The data recovery logic samples and low pass filters each incoming bit, thereby improv-

ing the noise immunity of the Receiver. The asynchronous reception operational range

depends on the accuracy of the internal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

Asynchronous Clock

Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-

ure 103 illustrates the sampling process of the start bit of an incoming frame. The

sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for

Double Speed mode. The horizontal arrows illustrate the synchronization variation due

to the sampling process. Note the larger time variation when using the Double Speed

mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD

line is idle (i.e., no communication activity).

Assembly Code Example

(1)

USART_Flush:

sbis

UCSRA, RXC0

ret

r16, UDR

rjmp

USART_Flush

C Code Example(1)

void

USART_Flush( void )

{

unsigned char

dummy;

while

( UCSRA & (1<<RXC0) ) dummy = UDR;

}

AT90PWM2 Datasheet(PDF) 206 Page - ATMEL Corporation

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