AT90PWM2 datasheet(204/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The receive function example reads all the I/O Registers into the Register File before

any computation is done. This gives an optimal receive buffer utilization since the buffer

location read will be free to accept new data as early as possible.

Receive Complete Flag and

Interrupt

The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXC) flag indicates if there are unread data present in the

receive buffer. This flag is one when unread data exist in the receive buffer, and zero

when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver

is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit

will become zero.

When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART

Receive Complete interrupt will be executed as long as the RXC flag is set (provided

that global interrupts are enabled). When interrupt-driven data reception is used, the

receive complete routine must read the received data from UDR in order to clear the

RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags

The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and

Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags

is that they are located in the receive buffer together with the frame for which they indi-

cate the error status. Due to the buffering of the error flags, the UCSRA must be read

before the receive buffer (UDR), since reading the UDR I/O location changes the buffer

read location. Another equality for the error flags is that they can not be altered by soft-

ware doing a write to the flag location. However, all flags must be set to zero when the

UCSRA is written for upward compatibility of future USART implementations. None of

the error flags can generate interrupts.

The Frame Error (FE) flag indicates the state of the first stop bit of the next readable

frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly

read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This

flag can be used for detecting out-of-sync conditions, detecting break conditions and

protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC

since the Receiver ignores all, except for the first, stop bits. For compatibility with future

devices, always set this bit to zero when writing to UCSRA.

AT90PWM2 Datasheet(PDF) 204 Page - ATMEL Corporation