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AT90PWM2 Datasheet(PDF) 257 Page - ATMEL Corporation

Part # AT90PWM2
Description  8-bit Microcontroller with 8K Bytes In-System Programmable Flash
PDF  365 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 257 Page - ATMEL Corporation

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257
AT90PWM2/3
4317B–AVR–02/05
ADC Register Description
The ADC of the AT90PWM2/3 is controlled through 3 different registers. The ADCSRA
and The ADCSRB registers which are the ADC Control and Status registers, and the
ADMUX which allows to select the Vref source and the channel to be converted.
The conversion result is stored on ADCH and ADCL register which contain respectively
the most significant bits and the less significant bits.
ADC Multiplexer Register –
ADMUX
• Bit 7, 6 – REFS1, 0: ADC Vref Selection Bits
These 2 bits determine the voltage reference for the ADC.
The different setting are shown in Table 100.
If these bits are changed during a conversion, the change will not take effect until this
conversion is complete (it means while the ADIF bit in ADCSRA register is set).
In case the internal Vref is selected, it is turned ON as soon as an analog feature
needed it is set.
• Bit 5 – ADLAR: ADC Left Adjust Result
Set this bit to left adjust the ADC result.
Clear it to right adjust the ADC result.
The ADLAR bit affects the configuration of the ADC result data registers. Changing this
bit affects the ADC data registers immediately regardless of any on going conversion.
For a complete description of this bit, see Section “ADC Result Data Registers – ADCH
and ADCL”, page 260.
• Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits
These 4 bits determine which analog inputs are connected to the ADC input. The differ-
ent setting are shown in Table 101.
Bit
7
65
43
21
0
REFS1
REFS0
ADLAR
-
MUX3
MUX2
MUX1
MUX0
ADMUX
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 100. ADC Voltage Reference Selection
REFS1
REFS0
Description
0
0
External Vref on AREF pin, Internal Vref is switched off
0
1
AVcc with external capacitor connected on the AREF pin
10
Reserved
1
1
Internal 2.56V Reference voltage with external capacitor connected
on the AREF pin
Table 101. ADC Input Channel Selection
MUX3
MUX2
MUX1
MUX0
Description
00
00
ADC0
00
01
ADC1
00
10
ADC2
00
11
ADC3
01
00
ADC4



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