AT90PWM2 datasheet(259/365 Pages) ATMEL

259 / 365 page

259

AT90PWM2/3

4317B–AVR–02/05

Set this bit to activate the ADC end of conversion interrupt.

Clear it to disable the ADC end of conversion interrupt.

• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits

These 3 bits determine the division factor between the system clock frequency and input

clock of the ADC.

The different setting are shown in Table 102.

ADC Control and Status

• Bit 7 – ADHSM: ADC High Speed Mode

Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to

convert with an ADC clock frequency higher than 200KHz.

• Bit 4– ADASCR: Analog to Digital Conversion on Amplified Channel Start

Conversion Request Bit

Set this to request a conversion on an amplified channel.

Cleared by hardware as soon as the Analog to Digital Conversion is started.

Alternatively, this bit can be cleared by writing it to logical zero.

• Bit 3, 2, 1, 0– ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits

These bits are only necessary in case the ADC works in auto trigger mode. It means if

ADATE bit in ADCSRA register is set.

In accordance with the Table 103, these 3 bits select the interrupt event which will gen-

erate the trigger of the start of conversion. The start of conversion will be generated by

the rising edge of the selected interrupt flag whether the interrupt is enabled or not. In

case of trig on PSCnASY event, there is no flag. So in this case a conversion will start

each time the trig event appears and the previous conversion is completed..

Table 102. ADC Prescaler Selection

ADPS2

ADPS1

ADPS0

Division Factor

128

Bit

ADHSM

ADASCR

ADTS3

ADTS2

ADTS1

ADTS0

ADCSRB

Read/Write

R/W

Initial Value

Table 103. ADC Auto Trigger Source Selection

ADTS3

ADTS2

ADTS1

ADTS0

Description

Free Running Mode

Analog Comparator 0

External Interrupt Request 0

AT90PWM2 Datasheet(PDF) 259 Page - ATMEL Corporation

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