AT90PWM2 datasheet(261/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

• Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is

disabled. The corresponding PIN Register bit will always read as zero when this bit is

set. When an analog signal is applied to the ADC7..0 pin and the digital input from this

pin is not needed, this bit should be written logic one to reduce power consumption in

the digital input buffer.

Digital Input Disable Register

1– DIDR1

• Bit 5:0 – ACMP0D, AMP0+D, AMP0-D, ADC10D..ADC8D: ACMP0, AMP1:0 and

ADC10:8 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is

disabled. The corresponding PIN Register bit will always read as zero when this bit is

set. When an analog signal is applied to an analog pin and the digital input from this pin

is not needed, this bit should be written logic one to reduce power consumption in the

digital input buffer.

Amplifier

The AT90PWM2/3 features two differential amplified channels with programmable 5, 10,

20, and 40 gain stage.

Because the amplifier is a switching capacitor amplifier, it needs to be clocked by a syn-

chronization signal called in this document the amplifier synchronization clock. To

ensure an accurate result, the amplifier input needs to have a quite stable input value

during at least 4 Amplifier synchronization clock periods.

Amplified conversions can be synchronized to PSC events (See “Synchronization

Source Description in One/Two/Four Ramp Modes” on page 168 and “Synchronization

Source Description in Centered Mode” on page 169) or to the internal clock CK

ADC equal

to eighth the ADC clock frequency. In case the synchronization is done the ADC clock

divided by 8, this synchronization is done automatically by the ADC interface in such a

way that the sample-and-hold occurs at a specific phase of CK

ADC2. A conversion initi-

ated by the user (i.e., all single conversions, and the first free running conversion) when

ADC2 is low will take the same amount of time as a single ended conversion (13 ADC

clock cycles from the next prescaled clock cycle). A conversion initiated by the user

when CK

ADC2 is high will take 14 A DC clock c ycles due to the synchronization

mechanism.

The normal way to use the amplifier is to select a synchronization clock via the

AMPxMX3:0 bits in the AMPxCSR register. Then the amplifier can be switched on, and

the amplification is done on each synchronization event.

In order to start an amplified Analog to Digital Conversion on the amplified channel, the

ADMUX must be configured as specified on Table 101 on page 257.

The ADC starting requirement is done by setting the ADASCR (Analog to Digital Con-

version on Amplified Channel Start Conversion Request ) bit in the ADCSRB register.

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ACMPM

ADC2D

ACMP2D

ADC1D

ADC0D

DIDR0

Read/Write

R/W

Initial Value

000

Bit

765

432

ACMP0D

AMP0PD

AMP0ND

ADC10D

ACMP1D

ADC9D

AMP1PD

ADC8D

AMP1ND

DIDR1

Read/Write

R/W

Initial Value

000

AT90PWM2 Datasheet(PDF) 261 Page - ATMEL Corporation

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