AT90PWM2 datasheet(264/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

Set this bit to enable the Amplifier 0.

Clear this bit to disable the Amplifier 0.

Clearing this bit while a conversion is running will take effect at the end of the

conversion.

• Bit 6– AMP0IS: Amplifier 0 Input Shunt

Set this bit to short-circuit the Amplifier 0 input.

Clear this bit to normally use the Amplifier 0.

• Bit 5, 4– AMP0G1, 0: Amplifier 0 Gain Selection Bits

These 2 bits determine the gain of the amplifier 0.

The different setting are shown in Table 104.

To ensure an accurate result, after the gain value has been changed, the amplifier input

needs to have a quite stable input value during at least 4 Amplifier synchronization clock

periods.

• Bit 1, 0– AMP0TS1, AMP0TS0: Amplifier 0 Trigger Source Selection Bits

In accordance with the Table 105, these 2 bits select the event which will generate the

trigger for the amplifier 0. This trigger source is necessary to start the conversion on the

amplified channel.

Amplifier 1Control and Status

• Bit 7 – AMP1EN: Amplifier 1 Enable Bit

Set this bit to enable the Amplifier 1.

Clear this bit to disable the Amplifier 1.

Clearing this bit while a conversion is running will take effect at the end of the

conversion.

• Bit 6– AMP1IS: Amplifier 1 Input Shunt

Set this bit to short-circuit the Amplifier 1 input.

Clear this bit to normally use the Amplifier 1.

Table 104. Amplifier 0 Gain Selection

REFS1

REFS0

Description

Gain 5

Gain 10

Gain 20

Gain 40

Table 105. AMP0 Auto Trigger Source Selection

AMP0TS1

AMP0TS0

Description

Auto synchronization on ADC Clock/8

Trig on PSC0_ASY

Trig on PSC1_ASY

Trig on PSC2_ASY

Bit

AMP1EN

AMP1IS

AMP1G1

AMP1G0

AMP1TS1

AMP1TS0

AMP1CSR

Read/Write

R/W

Initial Value

AT90PWM2 Datasheet(PDF) 264 Page - ATMEL Corporation

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