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AT90PWM2 Datasheet(PDF) 260 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 260 Page - ATMEL Corporation |
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260 / 365 page  260 AT90PWM2/3 4317B–AVR–02/05 ADC Result Data Registers – ADCH and ADCL When an ADC conversion is complete, the conversion results are stored in these two result data registers. When the ADCL register is read, the two ADC result data registers can’t be updated until the ADCH register has also been read. Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH. Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read ADCH to have the conversion result. ADLAR = 0 ADLAR = 1 Digital Input Disable Register 0 – DIDR0 0 0 1 1 Timer/Counter0 Compare Match 0 1 0 0 Timer/Counter0 Overflow 0 1 0 1 Timer/Counter1 Compare Match B 0 1 1 0 Timer/Counter1 Overflow 0 1 1 1 Timer/Counter1 Capture Event 1 0 0 0 PSC0ASY Event 1 0 0 1 PSC1ASY Event 1 0 1 0 PSC2ASY Event 1 0 1 1 Analog comparator 1 1 1 0 0 Analog comparator 2 11 01 Reserved 11 10 Reserved 11 11 Reserved Table 103. ADC Auto Trigger Source Selection ADTS3 ADTS2 ADTS1 ADTS0 Description Bit 7 65 43 21 0 - - ---- ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write R R R R R R R R R RRR R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 00 00 Bit 7 65 43 21 0 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 - - - - - - ADCL Read/Write R R R R R R R R R RRR R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 00 00 Bit 765 432 10 |
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