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AT90PWM2 Datasheet(PDF) 262 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 262 Page - ATMEL Corporation |
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262 / 365 page ![]() 262 AT90PWM2/3 4317B–AVR–02/05 Then, the ADSC bit of the ADCSRA Register is set on the next amplifier clock event, and a conversion is started. Until the conversion is not achieved, it is not possible to start a conversion on another channel. In order to have a better understanding of the functioning of the amplifier synchroniza- tion, a timing diagram example is shown Figure 129. Figure 129. Amplifier synchronization timing diagram It is also possible to auto trigger conversion on the amplified channel. In this case, the conversion is started at the next amplifier clock event following the last auto trigger event selected thanks to the ADTS bits in the ADCSRB register. In auto trigger conver- sion, the free running mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion. Valid sample Delta V 4th stable sample Signal to be measured AMPLI_clk (Sync Clock) CK ADC Amplifier Sample Enable Amplifier Hold Value PSCn_ASY PSC Block Amplifier Block ADASCR ADSC ADC ADC Result Ready ADC Sampling |
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