| Electronic Components Datasheet Search |
|
AT90PWM2 Datasheet(PDF) 265 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT90PWM2 Datasheet(HTML) 265 Page - ATMEL Corporation |
|
265 / 365 page ![]() 265 AT90PWM2/3 4317B–AVR–02/05 • Bit 5, 4– AMP1G1, 0: Amplifier 1 Gain Selection Bits These 2 bits determine the gain of the amplifier 0. The different setting are shown in Table 106. To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least 4 Amplifier synchronization clock periods. • Bit 1, 0– AMP1TS1, AMP1TS0: Amplifier 1 Trigger Source Selection Bits In accordance with the Table 107, these 2 bits select the event which will generate the trigger for the amplifier 1. This trigger source is necessary to start the conversion on the amplified channel. Table 106. Amplifier 1 Gain Selection REFS1 REFS0 Description 00 Gain 5 01 Gain 10 10 Gain 20 11 Gain 40 Table 107. AMP1 Auto Trigger source selection AMP1TS1 AMP1TS0 Description 0 0 Auto synchronization on ADC Clock/8 0 1 Trig on PSC0_ASY 1 0 Trig on PSC1_ASY 1 1 Trig on PSC2_ASY |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |