Quintuple/Triple-Output TFT LCD Power Supplies

with Fault Protection and VCOM Buffer

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11

PIN

MAX1997

MAX1998

NAME

FUNCTION

4

—

FB1

Logic Linear-Regulator (REG 1) Feedback Input. FB1 regulates at 1.25V nominal. Connect

FB1 to the center tap of a resistive voltage-divider between the REG 1 output and the analog

ground (GND) to set the output voltage. Place the resistive voltage-divider close to the pin.

52

CT

Sequence Timing Control Input. Connect a capacitor from this pin to GND. This timing

capacitor controls the turn-on of REG P, REG N, REG 2, and DRVA. The sequence timing

block is enabled, together with the main step-up regulator, when ONDC goes high. Then an

on delay. A discharge switch keeps CT at GND when the sequence timing block is disabled.

(See the Power-Up Sequencing and Inrush Current Control section.)

63

ONN

Gate-Off Linear-Regulator (REG N) Sequence Control Input. REG N is enabled when SHDN is

the Power-Up Sequencing and Inrush Current Control section.)

74

ONP

Gate-On Linear-Regulator (REG P) Sequence Control Input. REG P is enabled when SHDN is

the Power-Up Sequencing and Inrush Current Control section.)

85

ON2

Gamma Linear-Regulator (REG 2) Sequence Control Input. REG 2 is enabled when SHDN is

also controls the DRVA open-drain output, which is typically used to turn on an N-channel

MOSFET between the step-up regulator output and the source driver ICs’ supply pins. (See

the Power-Up Sequencing and Inrush Current Control section.)

9

6

DRVN

Gate-Off Linear-Regulator (REG N) Base Drive. Open drain of an internal P-channel MOSFET.

Connect DRVN to the base of an external NPN linear regulator pass transistor. (See the Pass

Transistor Selection section.)

10

7

FBN

Gate-Off Linear-Regulator (REG N) Feedback Input. FBN regulates to 125mV nominal. Connect

FBN to the center tap of a resistive voltage-divider between the REG N output and the reference

voltage (REF) to set the output voltage. Place the resistive voltage-divider close to the pin.

11

8

DRVA

Open-Drain Sequence Output. The DRVA open-drain output is controlled by ON2. DRVA is

typically used to turn on an N-channel MOSFET between the step-up regulator output and the

source-driver ICs’ supply pins. DRVA is high impedance when SHDN is high, the gate to the

to ground. (See the Power-Up Sequencing and Inrush Current Control section.)

12

9

REF

Internal Reference Bypass Terminal. Connect a 0.22µF ceramic capacitor from REF to the

analog ground (GND). External load capability is at least 75µA.

13

10

GND

Analog Ground.

14

—

FBNB

VCOM Buffer Inverting Input. (See the VCOM Buffer section.)

15

—

OUTB

VCOM Buffer Output. Requires a minimum 0.47µF ceramic filter capacitor to GND. Place the

capacitor as close as possible to OUTB.

16

—

VCOM Buffer Supply Input. Bypass to GND with a 0.47µF capacitor as close as possible to

the pin.

17

—

FBPB

VCOM Buffer Noninverting Input. (See the VCOM Buffer section.)

18

—

FB2

Gamma Linear-Regulator (REG 2) Feedback Input. FBP regulates to 1.25V nominal. Connect

FB2 to the center tap of a resistive voltage-divider between the REG 2 output and the analog

ground (GND) to set the output voltage. Place the divider close to the pin.

Pin Description (continued)