MAX1997 datasheet(29/31 Pages) MAXIM

29 / 31 page

Quintuple/Triple-Output TFT LCD Power Supplies

with Fault Protection and VCOM Buffer

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Applications Information

PC Board Layout and Grounding

Careful PC board layout is extremely important for

proper operation. Use the following guidelines for good

PC board layout:

1) The high-current loops of the main step-up regula-

tors are shown in Figure 12. Minimize the area of

these loops by placing the input bypass capacitors,

output diode, and output capacitors less than 0.2in

(5mm) from the LX and PGND pins. Connect these

components with traces as wide as possible. Avoid

using vias in the high-current paths. If vias are

unavoidable, use many vias in parallel to reduce

resistance and inductance.

2) Create islands for the analog ground (GND), power

ground (PGND), and linear-regulator ground.

Connect all three ground areas (islands) at only one

location, which is the backside pad of the device.

The REF bypass capacitor and all feedback dividers

should be connected to the analog ground island

(GND). The step-up regulator’s input and output

capacitors, and the charge-pump components

should be a wide power ground plane. The power

ground plane should be connected to the power

ground pin (PGND) with a wide trace. Maximizing

the width of the power ground traces improves effi-

ciency and reduces output voltage ripple and noise

spikes. All the other ground connections, such as

the IN pin bypass capacitor and the linear-regulator

output capacitors, should be star-connected to the

backside of the device with wide traces. Make no

other connections between these separate ground

planes.

3) Place the IN pin and REF pin bypass capacitors as

close to the device as possible.

4) Place all feedback voltage-divider resistors as

close to their respective feedback pins as possible.

The divider’s center trace should be kept short.

Placing the resistors far away causes their FB

traces to become antennas that can pick up switch-

ing noise. Care should be taken to avoid running

any feedback trace parallel to its associated drive

trace or near LX or the switching nodes in the

charge pumps.

5) Minimize the length and maximize the width of the

traces between the output capacitors and the load

for best transient responses.

6) Minimize the size of the LX node while keeping it

wide and short. Keep the LX node away from feed-

back nodes (FB, FBP, and FBN) and analog

ground. Use DC traces as a shield, if necessary.

Large ground planes on a multilayer board can pro-

vide additional shielding.

Refer to the MAX1997 evaluation kit for an example of

proper board layout.

Additional Application Circuits

Operation with Main Output Voltage >13V

The maximum output voltage of the step-up regulator is

13V, which is limited by the absolute maximum rating of

the internal power MOSFET. To achieve higher output

voltage, an external N-channel MOSFET can be cas-

coded with the internal FET (Figure 13). Since the gate

of the external FET is biased from the input supply, use

a logic-level FET to ensure that the FET is fully

enhanced at the minimum input voltage. The current

rating of the FET needs to be higher than the internal

current limit.

Disabling Input MOSFET Switch

If the input protection MOSFET is not needed, disable

the input overcurrent comparator by connecting the

OCP pin to ground, and the OCN pin to REF. Leave the

GATE pin floating (Figure 14).

Figure 14. Disabling Input MOSFET Switch

MAX1997

MAX1998

STEP-UP

REGULATOR

SWITCH

CONTROL

REF

GATE

3.3V TO 5V

OCN

OCP

OCN

GND

PGND

VMAIN

+9V

VIN

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