MAX1997 datasheet(20/31 Pages) MAXIM

20 / 31 page

Quintuple/Triple-Output TFT LCD Power Supplies

with Fault Protection and VCOM Buffer

______________________________________________________________________________________

Input Overcurrent Protection

The high-side overcurrent comparator of the

MAX1997/MAX1998 provides input overcurrent protec-

tion when it is used together with the external P-channel

MOSFET switch P1 (Figure 1). Connect resistive volt-

age-dividers from the source and drain of P1 to GND to

set the overcurrent threshold. The center taps of the

dividers are connected to the overcurrent comparator

inputs (OCN and OCP). See Setting the Input

Overcurrent Threshold section for information on calcu-

lating the resistor values. An overcurrent event acti-

vates the fault-protection circuitry. (See the Fault

Protection section.)

Fault Protection

During steady-state operation, if the output of the main

regulator or any of the linear-regulator outputs is below

its respective fault detection threshold, or an input over-

current condition occurs, the MAX1997/MAX1998 acti-

vate an internal fault timer (Figure 8). If any condition or

the combination of conditions indicates a continuous

fault for the fault timer duration (see Table 3), the

MAX1997/MAX1998 set the fault latch, shutting down

all the outputs except the reference and the oscillator.

The fault detection circuit is disabled during the soft-

start time of each regulator. Once the fault condition is

removed, toggle SHDN (below 0.4V) or cycle the input

voltage (below 2.2V) to clear the fault latch and reacti-

vate the device.

Thermal Shutdown

The thermal shutdown feature limits total power dissipa-

tion in the MAX1997/MAX1998. If the junction tempera-

ture TJ exceeds +160

°C, a thermal sensor immediately

activates the fault protection (Figure 2) and sets the

fault latch, which shuts down all the outputs except the

reference, allowing the device to cool down. Once the

device cools down by at least 15

°C, the fault latch can

be cleared to reactivate the device. Toggling SHDN

(below 0.4V) or cycling the input voltage (below 2.2V)

clears the fault latch.

Design Procedure

Main Step-Up Regulator

Output Voltage Selection

Set the output voltage by connecting a resistive volt-

age-divider from the output (VMAIN) to GND with the

center tap connected to FB (see Figure 1). Select R8 to

be 1.5k

Ω or less for optimized transient response. For

higher efficiency, increase R8 to 12k

Ω and add lag

compensation. (See the Feedback Compensation sec-

tion.) Calculate R7 with the following equation:

R7 = R8 [(VMAIN / VFB) - 1]

where VFB = 1.242V - (D x 20mV) and

≈ (VMAIN - VIN) / VMAIN.

For example, if VIN = 3V and D

≈ 0.66, then VFB =

1.229V.

Choosing 1.21k

Ω for R8, R7 is 7.65kΩ. Use 7.68kΩ for

R7. VMAIN can range from VIN to 13V.

Inductor Selection

The minimum inductance value, peak current rating,

series resistance, and size are factors to consider when

selecting the inductor. These factors influence the con-

verter’s efficiency, maximum output load capability, tran-

sient response time, and output voltage ripple. For a

switching frequency of 1.5MHz, use values between

1.8µH and 4.7µH. For a switching frequency of 750kHz,

use values between 3.3µH and 8.2µH. For a switching

frequency of 375kHz, use values between 6.8µH and

15µH.

FREQ PIN

PFLT PIN*

FAULT TIMER DURATION (CLOCK CYCLES)

FAULT TIMER DURATION (ms)

GND

21.8

Unconnected

GND

21.8

GND

21.8

GND

Unconnected

43.6

Unconnected

43.6

Unconnected

43.6

GND

IN**

87.2

Unconnected

IN**

87.2

IN**

87.2

Table 3. Fault Timer Duration

*For MAX1997 only.

**The MAX1998 has PFLT internally connected high.

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