MAX1997 datasheet(27/31 Pages) MAXIM

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Quintuple/Triple-Output TFT LCD Power Supplies

with Fault Protection and VCOM Buffer

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Stability Requirements

The MAX1997/MAX1998 linear-regulator controllers use

an internal transconductance amplifier to drive an

external pass transistor. The transconductance amplifi-

er, the pass transistor, the base-emitter resistor, and

the output capacitor determine the loop stability.

The transconductance amplifier regulates the output

voltage by controlling the pass transistor’s base cur-

rent. The total DC loop gain is approximately:

where VT is 26mV at room temperature, hFE is the pass

transistor’s DC current gain, and IBIAS is the current

through the base-to-emitter resistor (RBE). Each of the

four linear-regulator controllers is designed for a differ-

ent maximum output current so they have different out-

put drive currents and different bias currents (IBIAS).

Each controller’s bias current can be found in the

Electrical Characteristics. The current listed in the

Conditions column for the FB_ Regulation Voltage

specification is the individual controller’s bias current.

The base-to-emitter resistor for each controller should

be chosen to set the correct IBIAS:

The output capacitor and the load resistance create the

dominant pole in the system. However, the internal

amplifier delay, the pass transistor’s input capacitance,

and the stray capacitance at the feedback node create

additional poles in the system, and the output capacitor’s

ESR generates a zero. For proper operation, use the

following steps to ensure the linear regulator stability:

1) First, calculate the dominant pole set by the linear

regulator’s output capacitor and the load resistor:

where CLDO is the output capacitance of the LDO

and RLOAD is the load resistance corresponding to

the maximum load current.

The unity gain crossover of the linear regulator is:

fCROSSOVER = AV(LDO)fPOLE(LDO)

2) The pole caused by the internal amplifier delay is at

about 1MHz:

fPOLE(AMP)

≅ 1MHz

3) Next, calculate the pole set by the transistor’s input

capacitance, the transistor’s input resistance, and

the base-to-emitter pullup resistor:

Because RBE is much greater than RIN, the above

equation can be simplified:

where gm is the transconductance of the pass tran-

sistor, and fT is the transition frequency. Both para-

meters can be found in the transistor’s data sheet.

Therefore, the equation can be further simplified:

4) Next, calculate the pole set by the linear regulator’s

feedback resistance and the capacitance between

FB_ and GND (approximately 5pF including stray

capacitance):

and

5) Next, calculate the zero caused by the output

capacitor’s ESR:

where RESR is the equivalent series resistance of

CLDO.

ESR ZERO

LDO ESR

POLE FB

()_

(||

)

216

POLE FB

()_

(||

)

(||

)

(||

)

219

288

211

POLE(CIN)

hFE

POLE(CIN)

≈

POLE(CIN)

πCN R

(

POLE(LDO)

LDO LOAD

πCR

BIAS

V(LDO)

BIAS FE

LOAD

REF

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















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