Quintuple/Triple-Output TFT LCD Power Supplies

with Fault Protection and VCOM Buffer

12

______________________________________________________________________________________

PIN

MAX1997

MAX1998

NAME

FUNCTION

19

—

DRV2

Gamma Linear-Regulator (REG 2) Base Drive. Open drain of an internal N-channel MOSFET.

Connect DRV2 to the base of an external PNP linear regulator pass transistor. (See the Pass

Transistor Selection section.)

20

11

FB

Main Step-Up Regulator Feedback Input. Connect FB to the center tap of a resistive voltage-

up regulator output voltage. (See the Main Step-Up Regulator, Output Voltage Selection

section.) Place the resistive voltage-divider close to the pin.

21

12

FBP

Gate-On Linear-Regulator (REG P) Feedback Input. FBP regulates to 1.25V nominal. Connect

FBP to the center tap of a resistive voltage-divider between the REG P output and the analog

ground (GND) to set the output voltage. Place the resistive voltage-divider close to the pin.

22

13

DRVP

Gate-On Linear-Regulator (REG P) Base Drive. Open drain of an internal N-channel MOSFET.

Connect DRVP to the base of an external PNP linear-regulator pass transistor. (See the Pass

Transistor Selection section.)

23

14

LX

Switching Node. Drain of the internal N-channel power MOSFET for the main step-up

regulator.

24

15

TGNDA

Internal Connection. Connect this pin to ground. Do not leave this pin floating.

25

16

OCN

Overcurrent Comparator Inverting Input. Connect OCN to the center tap of a resistive

voltage-divider connected to the drain of the external input protection P-channel MOSFET.

(See the Input Overcurrent Protection section.) If unused, connect OCN to REF.

26

17

OCP

Overcurrent Comparator Noninverting Input. Connect OCP to the center tap of a resistive

voltage-divider connected to the source of the external input protection P-channel MOSFET.

The voltage on OCP sets the input overcurrent threshold. (See the Input Overcurrent

Protection section.) If unused, connect OCP to GND.

27

18

GATE

Gate-Drive Output to the External Input Protection P-Channel MOSFET. (See the Input

Overcurrent Protection section.) If unused, leave GATE unconnected.

28

—

PFLT

Fault Timer Select Input. Pull PFLT above its logic high threshold (0.7

delay period to 87ms. Pull PFLT below its logic low threshold (0.3

period to 22ms. Leave PFLT unconnected to set the fault delay period to 44ms. The fault

delay period for the MAX1998 is fixed at 87ms.

29

19

IN

Supply Input. The supply voltage powers all the control circuitry. The input voltage range is

from 2.7V to 5.5V. Bypass IN to GND with a 0.47µF ceramic capacitor. Place the capacitor

within 5mm of IN.

30

—

ONDC

Step-Up Regulator Logic Control Input. The step-up regulator, VCOM buffer, and the sequence

timing block are enabled when ONDC is high and disabled when ONDC is low.

31

20

FREQ

Frequency Select Input. Pull FREQ above its logic high threshold (0.7

step-up regulator switching frequency to 1.5MHz. Pull FREQ below its logic low threshold

(0.3

to 750kHz.

32

—

SHDN

Active-Low Shutdown Control Input. All the sections of the device are disabled and the GATE

pin goes high when SHDN is below its 0.4V logic low threshold. Pull SHDN above its 1.6V

logic high threshold to enable the device. Do not leave SHDN unconnected.

Pin Description (continued)