LTM8045 datasheet(33/54 Pages) AD

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LTM4655

Rev. 0

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The input capacitance, CDn, is needed to filter the pulsed

current drawn by MTn. To prevent excessive voltage sag

on VDn, a low-effective series resistance (low-ESR) input

capacitor should be used, sized appropriately for the

maximum CDn RMS ripple current (see Equation 24).

ICDn(RMS) =InPK • Dn •(1–Dn)

(24)

ICDn(RMS) is maximum for Dn = 1/2. For Dn = 1/2,

ICDn(RMS) = 1/2 • InPK or 3A. This simplification of the

worst-case condition is commonly used for design pur-

poses because even significant deviations in Dn do not

offer much relief, in practice. Furthermore: note that ripple

current ratings from capacitor manufacturers are often

based on 2000 hours of life; therefore, it is advisable to

significantly over-design CDn, and/or choose a capacitor

rated at a higher temperature than required. Err on the

side of caution and contact the capacitor manufacturer to

understand the capacitor vendor’s derating methodology.

Several capacitors may be paralleled to meet the appli-

cation’s target size, height, and CDn RMS ripple current

rating. For lower input voltage applications, sufficient bulk

input capacitance is needed for CINLn to counteract line

sag and transient effects during output load changes.

Suggested values for CDn and CINHn are found in Table 12.

Take note that CDn is connected from VDn to VOUTn–,

whereas CINHn and CINLn are connected from VINn to

power ground; this is deliberate.

A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM4655’s VINn,

SVINn, and VDn pins. A ceramic input capacitor combined

with trace or cable inductance forms a high Q (under-

damped) tank circuit. If the LTM4655 circuit is plugged

into a live supply, the input voltage can ring to twice its

nominal value, possibly exceeding the device’s rating.

This situation is easily avoided; see the Hot Plugging

Safely section.

Output Capacitors, Negative-VOUT– Operation

Output capacitors COUTHn and COUTLn are applied across

the LTM4655’s VOUTn+/VOUTn– power output pins: suffi-

cient capacitance and low ESR are called for, to meet the

output voltage ripple, loop stability, and transient require-

ments. COUTLn can be a low ESR tantalum or polymer

capacitor. COUTHn is a ceramic capacitor. The typical out-

put capacitance is 22μF (type X5R material, or better), if

ceramic-only output capacitors are used.

For highest reliability designs, polarized output capaci-

tors (COUTLn) are not recommended, as there is a pos-

sibility of a diode-drop of reverse voltage appearing tran-

siently on VOUTn– during rapid application of input volt-

age or when RUN

n is toggled logic high (see Figure 49).

When polarized capacitors are used on VOUTn–, contact

the capacitor vendor to understand what reverse volt-

age their polarized capacitor can withstand. Be advised,

polarized capacitor reverse voltage rating is sometimes

temperature-dependent.

Output voltage ripple (∆VOUTn(PK-PK)–) is governed by

charge lost in COUTHn and COUTLn while MTn is on, in

addition to the contribution of a resistive drop across

the ESR of the output capacitors. This is expressed by

Equation 25.

ΔVOUTn(PK–PK) ≈

ILOADn •D

COUTn •fSWn

ILOADn •ESRn

(25)

Table 12 shows a matrix of suggested output capacitors

optimized for transient step-loads that are 50% of the full

load capability for that combination of VINn, VOUTn–, and

fSW. The table optimizes total equivalent ESR and total

bulk capacitance to yield the stated transient-load per-

formance. Additional output filtering may be required by

the system designer, if further reduction of output ripple

or dynamic transient spike is required. The LTpowerCAD

design tool is available for transient and stability analysis.

Optional Diodes to Guard Against Overstress,

Negative-VOUT– Operation

Just prior to output voltage start-up, a mechanism exists

whereby a diode-drop of reverse polarity can appear on

VOUTn–. See the Simplified Block Diagram and observe:

just prior to output voltage start-up, SVINn bias current

(ISVINn) flows through the module’s control IC, to SVOUTn–;

from there, the bias current (now ISVOUTn–) flows into

VOUTn– and through MBn’s body diode, to SWn. This cur-

rent (now ILn) continues to flow—though the 4μH power

inductor—to VOUTn+ and thus ground, closing the con-

trol IC bias circuit’s path. It is this current through MBn’s

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