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LTM8045 Datasheet(PDF) 27 Page - Analog Devices |
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LTM8045 Datasheet(HTML) 27 Page - Analog Devices |
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27 / 54 page ![]() LTM4655 27 Rev. 0 For more information www.analog.com A default value of CSSn = 1.5nF can be implemented by connecting ISET na to ISETnb. For other ramp-up rates, connect an external CSS capacitor parallel to RISET. When starting up into a pre-biased VOUT, the LTM4655 stays in a sleep mode, keeping MTn and MBn off until VISETna equals VOSNSn+—after which, the DC/DC con- verter commences switching action and VOUT is ramped according to the voltage commanded by ISET na. Since the LTM4655 control loop servos its VOSNSn+ volt- age to match that of ISET na’s, the LTM4655’s channel n output can be configured to track any voltage applied to ISET na, referenced to SVOUTn–. See Figure 52 for an example of the LTM4655 configured as a DAC-controlled bipolar-output programmable power supply. The LTM4655 can track the mirror-image of a posi- tive rail to generate the negative half of a split-sup- ply, as seen in Figure 50 (note the use of RTRACK and RISET2 = RISET1 || RTRACK). Frequency Adjustment The default switching frequency (fSWn) of channel n of the LTM4655 is 400kHz. This is suitable for low-VIN (VINn ≤ 5V) applications and low-VOUT (VOUTn+ – VOUTn– ≤ 3.3V) applications. For a practical design, the LTM4655’s induc- tor ripple current (∆InPK-PK) is suggested to be less than ~2APK-PK. Choose fSWn according to Equation 11. fSWn = VOUTn+ − VOUTn− • 1−Dn ( ) Ln • ∆InPK-PK (11) where the value of LTM4655’s power inductor, Ln, is 4μH. To avoid cycle-skipping, impose restrictions on fSWn, to ensure minimum on-time criteria is met (Equation 12). fSWn < Dn TONn(MIN) (12) RfSETn NOT USED RfSETn (kΩ) 10 100 1k 10k 0.1 1 10 4655 F01 Figure 1. Relationship Between RfSETn and Target fSWn The LTM4655’s minimum on-time, tONn(MIN), is specified as 60ns. For a practical design, it is recommended to guardband to 90ns. To configure channel n of the LTM4655 for a higher switching frequency than its default of 400kHz, apply a resistor, RfSETn, between the fSETn pin and SVOUTn+. RfSETn is given (in MΩ) by Equation 13. RfSETn(MΩ)= 1 10pF •[fSWn(MHz)–0.4(MHz)] (13) The relationship of RfSETn to programmed fSWn is shown in Figure 1. See Table 11 and Table 12 for recommended fSWn and corresponding RfSETn values for various com- binations of VINn, VOUTn+ and VOUTn–. OPERATION |
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