LTM8045 datasheet(36/54 Pages) AD

36 / 54 page

LTM4655

Rev. 0

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APPLICATIONS INFORMATION

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal oper-

ating conditions of a µModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4655, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to differ-

ent junctions of components or die are not exactly linear

with respect to total package power loss. To reconcile this

complication without sacrificing modeling simplicity—

but also not ignoring practical realities—an approach has

been taken using FEA software modeling along with labo-

ratory testing in a controlled-environment chamber to rea-

sonably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4655 and the specified PCB with all of the correct

material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JESD51-9 and

JESD51-12 to predict power loss heat flow and

temperature readings at different interfaces that enable

the calculation of the JEDEC-defined thermal resistance

values; (3) the model and FEA software is used to evaluate

the LTM4655 with heat sink and airflow; (4) having solved

for and analyzed these thermal resistance values and

simulated various operating conditions in the software

model, a thorough laboratory evaluation replicates the

simulated conditions with thermocouples within a con-

trolled environment chamber while operating the device

at the same power loss as that which was simulated. The

outcome of this process and due diligence yields the set

of derating curves provided in later sections of this data

sheet, along with well-correlated JESD51-12-defined θ

values provided in the Pin Configuration section.

For positive-VOUT applications, the 12VIN and 24VIN power

loss curves in Figure 11 and Figure 12, respectively, can

be used with the load current derating curves in Figure 13

to Figure 24 for calculating an approximate θJA thermal

resistance for the LTM4655 with various heat sinking

and air flow conditions. For negative-VOUT applications:

use instead the –5VOUT, –12VOUT and –24VOUT power

loss curves in Figure 25 to Figure 27, respectively, in

combination with the load current derating curves in

Figure 28 to Figure 43. For split-supply applications,

total power loss within the module will dictate the thermal

derating; interpolate the relevant derating curves. These

thermal resistances represent demonstrated performance

of the LTM4655 on DC2898A and DC2899A hardware;

4-layer FR4 PCB measuring 97mm × 116mm × 1.6mm

using outer and inner copper weights of 2oz and 1oz,

Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients

4655 F10

µModule DEVICE

θJCtop JUNCTION-TO-CASE

(TOP) RESISTANCE

θJA JUNCTION-TO-AMBIENT RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

θJCbot JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

LTM8045 Datasheet(PDF) 36 Page - Analog Devices

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