LTM8045 datasheet(46/54 Pages) AD

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LTM4655

Rev. 0

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APPLICATIONS INFORMATION

Safety Considerations

The LTM4655 does not provide galvanic isolation from

VINn to VOUTn+/VOUTn–. There is no internal fuse. If

required, a slow blow fuse with a rating twice the maxi-

mum input current needs to be provided to protect the

unit from catastrophic failure.

The fuse or circuit breaker, if used, should be selected to

limit the current to the regulator in case of a MTn MOSFET

fault. If MTn fails, the system’s input supply will source

very large currents to VOUTn+ through MTn. This can cause

excessive heat and board damage depending on how

much power the input voltage can deliver to this system.

A fuse or circuit breaker can be used as a secondary fault

protector in this situation. Each channel of the LTM4655

features its own, independent overcurrent and overtem-

perature protection.

Layout Checklist/Example

The high integration of LTM4655 makes the PCB board

layout straightforward. However, to optimize its electrical

and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current paths,

including VINn, VOUTn+ and VOUTn–. Doing so helps to

minimize the PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output (and, if

used, input-to-output) capacitors next to the VINn, VDn,

VOUTn+/VOUTn– pins to minimize high frequency noise.

• Place a dedicated power ground layer underneath the

LTM4655.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put vias directly on pads, unless they are capped

or plated over.

• For each channel, use a separate SVOUTn– copper plane

for components connected to signal pins. Connect

SVOUTn– to VOUTn– directly under the module.

• For parallel applications, connect the respective VOUTn+,

VOUTn–, VOSNSn+, RUNn, ISETna, COMPna, PGOODn

and IMON

na pins, accordingly (see Figure 45).

• Bring out test points on the signal pins for monitoring.

Figure 44 gives a good example of the recommended

LTM4655 layout.

Figure 44. Recommended PCB Layout, Package Top View

VOUT2–

VOUT1–

VOUT1+

VOUT1–

VOUT2+

VIN1

VIN2

4655 F44

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