LTM8045 datasheet(25/54 Pages) AD

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LTM4655

Rev. 0

For more information www.analog.com

IMON

na pin does not support such a feature and must be

connected to VOUTn–.) When IMONna is electrically con-

nected to IMON

nb, the voltage on the IMONna/IMONnb

node is proportional to load current—with 1V correspond-

ing to 4A load. If desired, IMON

na can be interfaced to an

external parallel RC network instead of the one provided by

IMON

nb. If IMONna ever exceeds 2V, a servo loop reduces

the LTM4655’s output current in order to keep IMON

at or below 2V. Through this servo mechanism, a parallel

RC network can be connected to IMON

na to implement an

average current limit function—if desired. When the feature

is not needed, connect IMON

na to VOUTn–.

The LTM4655 features an additional control pin called

VINREG

n, which has a 2V servo threshold. This pin can be

used to as an extra control pin, e.g., to reduce channel input

current draw during input line sag (“brownout”) conditions.

Connect VINREG

ntoINTVCCn whenthisfeatureisnotneeded.

TEMP+ and TEMP– pins give access to a diode-con-

nected PNP transistor, making it possible to monitor the

LTM4655’s internal temperature—if desired.

External component selection is primarily determined by

the maximum load current and output voltage. Refer to

Table 11 and Table 12 and the Test Circuits for recom-

mended external component values.

VIN to VOUT Conversion Ratios

There are restrictions on the VIN to VOUT conversion ratios

that the LTM4655 can achieve. The maximum duty cycle

of the LTM4655 is 96% typical. The VIN to VOUT mini-

mum dropout voltage is a function of load current when

operating in high duty cycle applications. As an example,

VOUTn(24VDC) from the Electrical Characteristics table

highlights the LTM4655’s ability to regulate 24VOUT at up

to 4A from 29VIN, when running at a switching frequency,

fSW, of 1.5MHz.

At very low duty cycles, the LTM4655’s on-time of MT

each switching cycle should be designed to exceed the

LTM4655 control loop’s specified minimum on-time of

60ns, tON(MIN), (guardband to 90ns) see Equation 4.

fSWn

> TON(MIN)n

(4)

where Dn (unitless) is the duty-cycle of MTn, given by

Equation 5:

Dn =

VOUTn+ − VOUTn−

VINn− − VOUTn−

(5)

In rare cases where the minimum on-time restriction

is violated, the channel

n frequency of the LTM4655

automatically and gradually folds back down to approxi-

mately one-fifth of its programmed switching frequency

to allow VOUT to remain in regulation. See the Frequency

Adjustment section. Be reminded of Notes 2 and 3 in

the Electrical Characteristics section regarding output

current guidelines.

Input Capacitors, Positive-VOUT Operation

The LTM4655 achieves low input conducted EMI noise

due to tight layout and high frequency bypassing of

MOSFETs MTn and MBn within the module itself. A small

filter inductor (400nH) is integrated in the input line (from

VINn to VDn), providing further noise attenuation—again,

local to the switching MOSFETs. The VDn and VINn pins

are available for external input capacitors—CDn and

CINHn—to form a high-frequency π filter. As shown in

the Simplified Block Diagram, the ceramic capacitor CDn

on the LTM4655’s VDn pins handles the majority of the

RMS current into the DC/DC converter power stage and

requires careful selection, for that reason.

See Figure 7 through Figure 9 for demonstration of

LTM4655’s EMI performance, meeting the radiated emis-

sions requirements of EN55022B.

The input capacitance, CDn, is needed to filter the pulsed

current drawn by MTn. To prevent excessive voltage sag

on VDn, a low-effective series resistance (low-ESR, such

as an X7R ceramic) input capacitor should be used, sized

appropriately for the maximum CDn RMS ripple current

(Equation 6)

ICDn(RMS) =

IOUTn(MAX)

ηn%

• Dn •(1–Dn)

(6)

where ηn% is the estimated efficiency of the chan-

nel

n power module. (See Typical Performance

Characteristics graphs.)

OPERATION

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