LTM8045 datasheet(26/54 Pages) AD

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LTM4655

Rev. 0

For more information www.analog.com

Several capacitors may be paralleled to meet the appli-

cation’s target size, height, and CDn RMS ripple current

rating. For lower input voltage applications, sufficient bulk

input capacitance is needed to counteract line sag and

transient effects during output load changes. The bulk

capacitor can be a switcher-rated aluminum electrolytic

capacitor or a Polymer capacitor. Suggested values for

CDn and CINHn are found in Table 11.

A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM4655’s VINn,

SVINn, and VDn pins. A ceramic input capacitor combined

with trace or cable inductance forms a high Q (under-

damped) tank circuit. If the LTM4655 circuit is plugged

into a live supply, the input voltage can ring to twice its

nominal value, possibly exceeding the device’s rating.

This situation is easily avoided; see the Hot Plugging

Safely section.

Output Capacitors, Positive-VOUT Operation

Output capacitors COUTHn and COUTLn are applied across

the LTM4655’s VOUTn+/VOUTn– power output pins.

Sufficient capacitance and low ESR are called for, to

meet the output voltage ripple, loop stability, and tran-

sient requirements. COUTLn can be a low ESR tantalum

or polymer capacitor. COUTHn is a ceramic capacitor. The

typical output capacitance is 22μF (type X5R material, or

better), if ceramic-only output capacitors are used.

Table 11 shows a matrix of suggested output capacitors

optimized for 2A transient step-loads applied at 2A/μs.

Additional output filtering may be required by the system

designer, if further reduction of output ripple or dynamic

transient spike is required. The LTpowerCAD design tool is

available for transient and stability analysis. Stability crite-

ria are considered in the Table 11 matrix, and LTpowerCAD

is available for stability analysis. Multiphase operation will

reduce effective output ripple as a function of the num-

ber of phases. Application Note 77 discusses this noise

reduction versus output ripple current cancellation, but

the output capacitance should be considered carefully as a

function of stability and transient response. LTpowerCAD

can be used to calculate the output ripple reduction as the

number of implemented phases increases by N times.

External loop compensation can be applied from COMPna

to SVOUTn–, if needed, for transient response optimization.

Forced Continuous Operation

Leave the CLKIN

n pin open circuit to command chan-

nel

n of the LTM4655 for forced continuous operation.

In this mode, the control loop is allowed to command the

inductor peak current to approximately –1A, allowing for

significant negative average current. Clocking the CLKIN

pin at a frequency within ±40% of the target switching fre-

quency commanded by the fSETn pin synchronizes MTn’s

turn-on to the rising edge of the CLKIN

n pin.

Output Voltage Programming, Tracking and Soft-Start

The LTM4655 regulates its output voltage, VOUTn+ – VOUTn–,

according to the differential voltage present from ISET

na to

SVOUTn–. In most applications, the output voltage is set by

simply connecting a resistor, RISETn,fromISETnatoSVOUTn–,

according to Equation 7.

RISETn =

VOUTn+ − VOUTn−

50µA

(7)

Since the LTM4655 control loop servos its output voltage

according to the voltage between ISET

na and SVOUTn–:

placing a capacitor, CSSn, parallel to RISETn configures the

ramp-up rate of ISET

na and thus the output. In the time

domain, the output voltage ramp-up after the RUN

n pin is

toggled from low to high (t = 0s) is given by Equation 8.

VOUTn(t)+ VOUTn(t)− =IISETna •RISETn • 1–e

–

RISETn• CSSn

⎛

⎝

⎜

⎞

⎠

⎟

(8)

The soft-start time, tSS, is defined as the time it takes for

channel n’s output voltage to ramp from 0V to 90% of its

final value (Equation 9 or Equation 10)

tSSn = –RISETn •CSSn •In(1–0.9)

(9)

tSSn =2.3 •RISETn •CSSn

(10)

OPERATION

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