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LTM8045 Datasheet(PDF) 16 Page - Analog Devices

Part # LTM8045
Description  EN55022B Compliant 40V, Dual 4A or Single 8A Step-Down or 50W Inverting 關Module Regulator
PDF  54 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM8045 Datasheet(HTML) 16 Page - Analog Devices

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LTM4655
16
Rev. 0
For more information www.analog.com
INTVCC2 (G8): Channel 2 Internal Regulator, 3.3V Output
with Respect to VOUT2–. Channel 2 internal control circuits
and MOSFET drivers derive power from INTVCC2 bias.
Leave INTVCC2 open circuit. An LDO generates INTVCC2
from either SVIN2 or EXTVCC2, when RUN2 is logic high
(RUN2–GND > 1.2V). The INTVCC2 LDO is turned off when
RUN2 is logic low (RUN2–GND < 1.2V). (See EXTVCC2.)
EXTVCC1 (F3): External Bias, Auxiliary Input to the
INTVCC1 Regulator. When EXTVCC1–VOUT1– > 3.2V and
SVIN1 > 5V and RUN1–GND > 1.2V, the INTVCC1 LDO
derives power from EXTVCC1 bias instead of SVIN1. This
technique reduces LDO losses considerably, resulting in
a corresponding reduction in module junction tempera-
ture. For applications in which 4V < VOUT1+ – VOUT1– <
28V, connect EXTVCC1 to VOUT1+ through a 15Ω~110Ω
resistor and locally decouple EXTVCC1 to VOUT1– with a
1μF ceramic capacitor. Otherwise, connect EXTVCC1 to
VOUT1– or leave EXTVCC1 open circuit. See the Applications
Information section.
EXTVCC2 (F8): External Bias, Auxiliary Input to the
INTVCC2 Regulator. When EXTVCC2–VOUT2– > 3.2V and
SVIN2 > 5V and RUN2–GND >1.2V, the INTVCC2 LDO
derives power from EXTVCC2 bias instead of SVIN2. This
technique reduces LDO losses considerably, resulting in
a corresponding reduction in module junction tempera-
ture. For applications in which 4V < VOUT2+ – VOUT2– <
28V, connect EXTVCC2 to VOUT2+ through a 15Ω~110Ω
resistor and locally decouple EXTVCC2 to VOUT2– with a
1μF ceramic capacitor. Otherwise, connect EXTVCC2 to
VOUT2– or leave EXTVCC2 open circuit. See the Applications
Information section.
ISET1b (F1): 1.5nF Soft-Start Capacitor for Channel 1.
Connect ISET1b to ISET1a to achieve default soft-start
characteristics on channel 1, if desired. See ISET1a.
ISET2b (F6): 1.5nF Soft-Start Capacitor for Channel 2.
Connect ISET2b to ISET2a to achieve default soft-start
characteristics on channel 2, if desired. See ISET2a.
ISET1a (F2): Accurate 50μA Current Source. Positive
input to the error amplifier of channel 1. Connect a resis-
tor RISET1a = ((VOUT1+ – VOUT1–)/50μA) from this pin
to SVOUT1– local to the module to program the desired
channel 1 output voltage magnitude, VOUT1+ – VOUT1–. A
capacitor can be connected from ISET1a to SVOUT1– to
soft-start channel 1’s output voltage, i.e., reduce its start-
up inrush current. Connect ISET1a to ISET1b in order to
achieve default soft-start characteristics if desired. (See
ISET1b.)
In addition, the channel 1 output of the LTM4655 can
track a voltage applied to this pin. (See the Applications
Information section.)
ISET2a (F7): Accurate 50μA Current Source. Positive
input to the error amplifier of channel 1. Connect a resis-
tor RISET2a = ((VOUT2+ – VOUT2–)/50μA) from this pin
to SVOUT2– local to the module to program the desired
channel 2 output voltage magnitude, VOUT2+ – VOUT2–. A
capacitor can be connected from ISET2a to SVOUT2– to
soft-start channel 2’s output voltage, i.e., reduce its start-
up inrush current. Connect ISET2a to ISET2b in order
to achieve default soft-start characteristics if desired.
(See ISET2b.)
In addition, the channel 2 output of the LTM4655 can
track a voltage applied to this pin. (See the Applications
Information section.)
PGOOD1 (D1): Channel 1 Power Good Indicator, Open-
Drain Output Pin. PGOOD1 is high impedance when
PGDFB1–SVOUT1– is within approximately ±7.5% of
0.6V. PGOOD1 is pulled to GND when PGDFB1 is outside
this range.
PGOOD2 (D6): Channel 2 Power Good Indicator, Open-
Drain Output Pin. PGOOD2 is high impedance when
PGDFB2–SVOUT2– is within approximately ±7.5% of
0.6V. PGOOD2 is pulled to GND when PGDFB2 is outside
this range.
PIN FUNCTIONS



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