LTM8045 datasheet(15/54 Pages) AD

15 / 54 page

LTM4655

Rev. 0

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VOSNS1+ (G1, H1): Positive Voltage Sense Input for

Channel 1. Route a signal trace from VOSNS1+ to VOUT1+

at channel 1’s point-of-load (POL). This provides the feed-

back signal to channel 1’s control loop. In noisy environ-

ments, shield VOSNS1+ from electrical noise by sandwich-

ing the trace between PGND copper. Pins G1 and H1 are

electrically connected to each other internal to the mod-

ule, and thus it is only necessary to connect one VOSNS1+

pin to VOUT1+ at the POL. The remaining VOSNS1+ pin can

be used for redundant connectivity or routed to an ICT

test point for design-for-test considerations, as desired.

VOUT2– (A10–12, B10, C10, D10–11, E10–11, F10–11,

G9–11, H8, H10–12, J8–10, K9–12, L9–12, M9–12):

Negative Power Output of Channel 2. Either connect

VOUT2– to a PGND plane in noninverting step-down appli-

cations, where VOUT2+ is the regulated positive output

voltage—or, connect VOUT2+ to PGND in inverting buck-

boost applications, where VOUT2– is the regulated negative

output voltage.

SVOUT2– (E9, G7, H7): Signal Return of Channel 2. The

SVOUT2– pins are the reference node for channel 2’s con-

trol loop. A small island of SVOUT2– copper should be

extended from the module and used to shield sensitive

channel 2 pins and signals from noise—such as those

routing to fSET2, ISET2a/b, and COMP2a/b. All SVOUT2–

pins are connected to each other internal to the module.

Connect Pin H7 to VOUT2– directly under the LTM4655.

The remaining SVOUT2– pins can be used for redundant

connectivity or routed to an ICT test point for design-

for-test considerations, as desired. See the Applications

Information section for the layout checklist.

VOUT2+ (K6–8, L6–8, M6–8): Positive Power Output of

Channel 2. Bypass VOUT2+ to VOUT2– local to the mod-

ule with at least 1μF. The remainder of VOUT2+ to VOUT2–

bypass caps should be located near channel 2’s load.

Either connect VOUT2+ to a PGND plane in inverting buck-

boost applications, where VOUT2– is the regulated nega-

tive output voltage—or, connect VOUT2– to a PGND plane

noninverting step-down applications, where VOUT2+ is the

regulated positive output voltage.

VOSNS2+ (G6, H6): Positive Voltage Sense Input for

Channel 2. Route a signal trace from VOSNS2+ to VOUT2+

at channel 2’s point-of-load (POL). This provides the feed-

back signal to channel 2’s control loop. In noisy environ-

ments, shield VOSNS2+ from electrical noise by sandwich-

ing the trace between PGND copper. Pins G6 and H6 are

electrically connected to each other internal to the mod-

ule, and thus it is only necessary to connect one VOSNS2+

pin to VOUT2+ at the POL. The remaining VOSNS2+ pin can

be used for redundant connectivity or routed to an ICT

test point for design-for-test considerations, as desired.

GND (D4, D9, D12): Ground Pins. The logic thresholds

for RUN

n, PGOODn, and CLKINn are electrically referred

to GND. GND is also the reference voltage for the 5V-fixed

LDO and the CLKOUT

n clock generator. Connect all GND

pins to a solid ground plane, PGND.

RUN1 (F4): Channel 1 Run Control Pin. A voltage above

~1.2V (with respect to GND) commands the module to

regulate its output voltage. Undervoltage lockout (UVLO)

can be implemented by connecting RUN1 to the midpoint

node formed by a resistor divider between VIN1 and GND.

RUN1 features ~130mV of hysteresis.

RUN2 (F9): Channel 2 Run Control Pin. A voltage above

~1.2V (with respect to GND) commands the module to

regulate its output voltage. Undervoltage lockout (UVLO)

can be implemented by connecting RUN2 to the midpoint

node formed by a resistor divider between VIN2 and GND.

RUN2 features ~130mV of hysteresis.

INTVCC1 (G3): Channel 1 Internal Regulator, 3.3V Output

with Respect to VOUT1–. Channel 1 internal control circuits

and MOSFET drivers derive power from INTVCC1 bias.

Leave INTVCC1 open circuit. An LDO generates INTVCC1

from either SVIN1 or EXTVCC1, when RUN1 is logic high

(RUN1–GND > 1.2V). The INTVCC1 LDO is turned off when

RUN1 is logic low (RUN1–GND < 1.2V). (See EXTVCC1.)

PIN FUNCTIONS

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