AD9699 datasheet(32/121 Pages) AD

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Data Sheet

AD9699

PROGRAMMABLE FIR FILTERS

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Rev. 0 | 32 of 121

PROGRAMMING INSTRUCTIONS

Use the following procedure to set up the programmable FIR filter:

1. Enable the sample clock to the device.

2. Set the I path mode (I mode) and gain in Register 0x0DF8 and

available. Q Mode is not available on single-channel devices.

3. Wait at least 5 µs to allow the programmable filter to power up.

4. Program the I path coefficients to the internal shadow registers

as follows:

a. Program the XI coefficients in Register 0x0E00 to Register

0x0E2F (see Table 14 and Table 15).

b. Program the YI coefficients in Register 0x0F00 to Register

0x0F2F (see Table 14 and Table 15).

c. Program the tapped delay in Register 0x0F30 (note that this

step is optional).

5. Set the chip transfer bit using either of the following methods

(note that setting the chip transfer bit applies the programmed

shadow coefficients to the filter):

a. Via the register map using the write the chip transfer bit

(Register 0x000F = 0x01).

b. Via a GPIO pin, as follows:

1. Configure one of the GPIO pins as the chip transfer bit

in Register 0x0040 to Register 0x0042.

2. Toggle the GPIO pin to initiate the chip transfer (the

rising edge is triggered).

6. When the I path mode register changes in Register 0x0DF8, all

coefficients must be reprogrammed.

Table 12. Register 0x0DF8 Definition

Bits

Description

[7:3]

Reserved

[2:0]

Filter mode (I mode)

000: filters bypassed

001: real 24-tap filter (X only)

010: real 48-tap filter (X and Y together)

100: real set of two cascaded 24-tap filters (X then Y cascaded)

111: real 96-tap filter (X and Y together)

Table 13. Register 0x0DF9 Definition

Bits

Description

Reserved

[6:4]

Y filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Reserved

[2:0]

X filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Table 14 shows the coefficient tables in Register 0x0E00 to Regis-

ter 0x0F30. Note that all coefficients are Q1.15 format (sign bit + 15

fractional bits).

Table 14. I Coefficient Table (Device Selection = 0x1)1

Addr.

Single 24-Tap Filter (I Mode

[2:0] = 0x1)

Single 48-Tap Filter (I Mode

[2:0] = 0x2)

Two Cascaded 24-Tap Filters (I

Mode [2:0] = 0x4)

Single 96-Tap Filter (I Mode

[2:0] = 0x7)

0x0E00

XI C0 [7:0]

0x0E01

XI C0 [15:8]

0x0E02

XI C1 [7:0]

0x0E03

XI C1 [15:8]

…

0x0E2E

XI C23 [7:0]

0x0E2F

XI C23 [15:0]

0x0F00

Unused

YI C24 [7:0]

YI C0 [7:0]

YI C24 [7:0]

0x0F01

Unused

YI C24 [15:8]

YI C0 [15:8]

YI C24 [15:8]

0x0F02

Unused

YI C25 [7:0]

YI C1 [7:0]

YI C25 [7:0]

0x0F03

Unused

YI C25 [15:8]

YI C1 [15:8]

YI C25 [15:8]

…

0x0F2E

Unused

YI C47 [7:0]

YI C23 [7:0]

YI C47 [7:0]

0x0F2F

Unused

YI C47 [15:0]

YI C23 [15:0]

YI C47 [15:0]

0x0F30

Unused

1 XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.

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