AD9699 datasheet(3/121 Pages) AD

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Data Sheet

AD9699

GENERAL DESCRIPTION

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The AD9699 is a single, 14-bit, 3 GSPS analog-to-digital converter

(ADC). The device has an on-chip buffer and a sample-and-hold

circuit designed for low power, small size, and ease of use. This

product is designed to support applications capable of direct sam-

pling wide bandwidth analog signals of up to 5 GHz. The −3 dB

bandwidth of the ADC input is 9 GHz. The AD9699 is optimized

for wide input bandwidth, high sampling rate, excellent linearity, and

low power in a small package.

The ADC core features a multistage, differential pipelined architec-

ture with integrated output error correction logic. The ADC features

wide bandwidth inputs supporting a variety of user-selectable input

ranges. An integrated voltage reference eases design considera-

tions. The analog input and clock signals are differential inputs.

The ADC data outputs are internally connected to four digital down-

converters (DDCs) through a crossbar multiplexer (mux). Each

DDC consists of up to five cascaded signal processing stages: a

48-bit frequency translator (numerically controlled oscillator (NCO)),

and up to four half-band decimation filters. The NCO has the

option to select preset bands over the general-purpose input/output

(GPIO) pins, which enables the selection of up to three bands.

Operation of the AD9699 between the DDC modes is selectable via

serial peripheral interface (SPI)-programmable profiles.

In addition to the DDC blocks, the AD9699 has several functions

that simplify the automatic gain control (AGC) function in a com-

munications receiver. The programmable threshold detector allows

monitoring of the incoming signal power using the fast detect

control bits in Register 0x0245 of the ADC. If the input signal level

exceeds the programmable threshold, the fast detect indicator goes

high. Because this threshold indicator has low latency, the user can

quickly turn down the system gain to avoid an overrange condition

at the ADC input. In addition to the fast detect outputs, the AD9699

also offers signal monitoring capability. The signal monitoring block

provides additional information about the signal being digitized by

the ADC.

The user can configure the Subclass 1 JESD204B-based high

speed serialized output in a variety of one-lane, two-lane, four-lane,

and eight-lane configurations, depending on the DDC configuration

and the acceptable lane rate of the receiving logic device. Multi-

device synchronization is supported through the SYSREF± and

SYNCINB± input pins.

The AD9699 has flexible power-down options that allow significant

power savings when desired. All of these features can be program-

med using a 3-wire SPI.

The AD9699 is available in a Pb-free, 12 mm × 12 mm, 196-ball

BGA and is specified over the −40°C to +85°C ambient temperature

range. This product is protected by a U.S. patent.

Note that throughout this data sheet, multifunction pins, such as

FD/GPIO_A0, are referred to either by the entire pin name or by a

single function of the pin, for example, FD, when only that function

is relevant.

PRODUCT HIGHLIGHTS

1. Wide, input −3 dB bandwidth of 9 GHz supports direct RF

sampling of signals up to about 5 GHz.

2. Four integrated, wideband decimation filter and NCO blocks

supporting multiband receivers.

3. Fast NCO switching enabled through the GPIO pins.

4. An SPI controls various product features and functions to meet

specific system requirements.

5. Programmable fast overrange detection and signal monitoring.

6. On-chip temperature diode for system thermal management.

7. 12 mm × 12 mm, 196-ball BGA.

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